Atmel SAM4S Series, Preliminary Data Sheet

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11100B–ATARM–31-Jul-12
SAM4S Series [Preliminary]
Figure 25-9. Write Cycle
25.8.3.3 Write Cycle
The write_cycle time is defined as the total duration of the write cycle, that is, from the time
where address is set on the address bus to the point where address may change. The total write
cycle time is equal to:
NWE_CYCLE = NWE NWE NWE_HOLD
= NCS_WR NCS_WR NCS_WR_HOLD
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of Master Clock cycles. To ensure that the NWE and NCS timings are coherent, the user
must define the total write cycle instead of the hold timing. This implicitly defines the NWE hold
time and NCS (write) hold times as:
NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE
NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE
25.8.3.4 Null Delay Setup and Hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see
Figure 25-10 ). How-
ever, for devices that perform write operations on the rising edge of NWE or NCS, such as
SRAM, either a setup or a hold must be programmed.
A[23:0]
NCS
NWE_SETUP NWE_PULSE NWE_HOLD
MCK
NWE
NCS_WR_SETUP
NCS_WR_PULSE
NCS_WR_HOLD
NWE_CYCLE