Atmel AVR10004: RCB256RFR2 – Hardware User Manual [APPLICATION NOTE]
12
Address Name
Type
Description
0x18
Antenna gain
int8
Antenna gain [1/10dBi]
e.g.: 0x0A = 10d will indicate a gain of 1.0dBi. The values 00h and FFh are per
definition invalid. Zero or -0.1dBi has to be indicated as 0x01 or 0xFE
0x20
Board name
char[30] Textual board description
0x3E
CRC
uint16
16 bit CRC checksum, standard ITU-T generator polynomial G
16
(x) = x
16
+ x
12
+ x
5
+ 1
Note:
1. MAC addresses used for this package are Atmel property. The use of these MAC addresses for development
purposes is permitted.
Example ID EEPROM dump:
0000 FF 1C 00 14 19 25 04 00 00 00 00 00 7D 00 00 00 .....%......}...
0010 01 06 03 02 02 00 A9 A9 00 FF FF FF FF FF FF FF ................
0020 52 43 42 32 35 36 52 46 52 32 00 00 00 00 00 00 RCB256RFR2......
0030 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 D9 ..............(.
0040 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
0050 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
0060 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
0070 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF ................
4.6
External peripherals
The RCB is equipped with two 50mil connectors (EXT0/1) to mount the RCB on a variety of expansion boards (base
boards). The connectors provide access to all spare Atmel Atmega256RFR2 pins, including USART, TWI, ADC, and
PWM.
Make sure that any RCB base board that is used together with the RCB256RFR2 will not drive the TST signal (EXT1,
pin5) high during operation. The only occasion to drive the TST signal high is during parallel programming. Refer to
for detailed information. For normal operation, this signal must be left open or pulled to ground. For the unconnected
case, R9 will drive the pin low.
The Atmega256RFR2 does not integrate a memory controller like the Atmel Atmega1281V. A memory controller
function is to be emulated by hardware (ports A, B, and C) and software. This results in an I/O mapping if this
functionality is needed:
•
A memory data bus is emulated using port B
•
For the memory address bus emulation, only the upper four address lines can be controlled via port D. To
achieve that, the PD4..7 signals are routed to both connections, port D and C
•
#RD and #WR, if needed, are emulated by PE5 and PE4
The detailed pin mapping is shown in
). This table also provides mapping of existing Atmega1281V-based
RCBs.
