Atmel ICE50, User Manual

Page: 27 / 74

General Description
ICE50 User Guide 3-13
2523A–AVR–11/02
Notes: 1. tOHL = Time from clearing the PORT register to the output changes
2. tOLH = Time from setting the PORT register to the output changes
3. tIHL = Time from changing the input level to the PIN signal changes (high to low)
4. tILH = Time from changing the input level to the PIN signal changes (low to high)
Figure 3-19 shows the timing data for tristating/driving the IO pins. Table 3-4 shows
related typical data.
Figure 3-19. Timing Data
Notes: 1. tDZL = time from setting the DDR register to the output is driven low.
2. tDLZ = time from clearing the DDR register to the output is tristated.
3. tDZH = time from setting the DDR register to the output is driven high.
4. tDHZ = time from clearing the DDR register to the output is driven low.
The drive capability of the output buffers are ± 24 mA at 3V V
CC
. This slightly exceeds
the driving capability of the actual parts. The operating voltage range of the IO circuits
are 2 V
CC
to 5.5 V
CC
. At 2V V
CC
the buffers are able to sink 25 mA with a maximal output
low voltage (VOLmax) of 1V.
The hysteresis voltage for the input buffers are typically 0.8V at 3V V
CC
and 1.2V at 5.5V
V
CC
.
Table 3-3. Data Direction
Delay Typical Value (2V Target) Typical Value (5V Target)
t
OHL
(1)
13 ns 10 ns
t
OLH
(2)
13 ns 10 ns
t
IHL
(3)
13 ns 10 ns
t
ILH
(4)
13 ns 10 ns
Table 3-4. Timing Data
Delay Typical Value (2V target) Typical Value (5V target)
t
DZL
(1)
15 ns 15 ns
t
DLZ
(2)
15 ns 15 ns
t
DZH
(3)
15 ns 15 ns
t
DHZ
(4)
15 ns 15 ns
DDRxy
PORTxy
Pxy
t
DZL
t
DLZ
t
DZH
t
DHZ
High Z High Z High Z