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8331B–AVR–03/12
Atmel AVR XMEGA AU
STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then
the acknowledge action will be updated before the command is triggered.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
21.9.4
STATUS – Status register
• Bit 7
–
RIF: Read Interrupt Flag
This flag is set when a byte is successfully received in master read mode; i.e., no arbitration was
lost or bus error occurred during the operation. Writing a one to this bit location will clear RIF.
When this flag is set, the master forces the SCL line low, stretching the TWI clock period. Clear-
ing the interrupt flags will release the SCL line.
This flag is also cleared automatically when:
• Writing to the ADDR register
• Writing to the DATA register
• Reading the DATA register
• Writing a valid command to the CMD bits in the CTRLC register
• Bit 6
–
WIF: Write Interrupt Flag
This flagis set when a byte is transmitted in master write mode. The flag is set regardless of the
occurrence of a bus error or an arbitration lost condition. WIF is also set if arbitration is lost dur-
ing sending of a NACK in master read mode, and if issuing a START condition when the bus
state is unknown. Writing a one to this bit location will clear WIF. When this flag is set, the mas-
ter forces the SCL line low, stretching the TWI clock period. Clearing the interrupt flags will
release the SCL line.
The flag is also cleared automatically for the same conditions as RIF.
Table 21-5.
CMD bits description.
CMD[1:0]
Group
Configuration
MODE
Operation
00
NOACT
X
Reserved
01
START
X
Execute acknowledge action succeeded by
repeated START condition
10
BYTEREC
W
No operation
R
Execute acknowledge action succeeded by
a byte receive
11
STOP
X
Execute acknowledge action succeeded by
issuing a STOP condition
Bit
7
6
5
4
3
2
1
0
RIF
WIF
CLKHOLD
RXACK
ARBLOST
BUSERR
BUSSTATE[1:0]
STATUS
Read/Write
R/W
R/W
R
R
R/W
R/W
R/W
R/W
Initial Value
0
0
0
0
0
0
0
0
