24
8331B–AVR–03/12
Atmel AVR XMEGA AU
4.8
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which are used to transfer data between
the 32 registers in the register file and the I/O memory. The IN and OUT instructions can
address I/O memory locations in the range of 0x00 0x3F directly. In the address range 0x00 -
0x1F, single-cycle instructions for manipulation and checking of individual bits are available.
4.8.1
General Purpose I/O Registers
The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These reg-
isters can be used for storing global variables and flags, as they are directly bit-accessible using
the SBI, CBI, SBIS, and SBIC instructions.
4.9
External Memory
Up to four ports are dedicated to external memory, supporting external SRAM, SDRAM, and
memory mapped peripherals such as LCD displays. For details, refer to
. The external memory address space will always start at the end of inter-
nal SRAM.
4.10
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus mas-
ters (CPU, DMA controller read and DMA controller write, etc.) can access different memory
sections at the same time. See
. The USB module acts as a bus master
and is connected directly to internal SRAM through a pseudo-dualport (PDP) interface.
Figure 4-3.
Bus access.
Peripherals and system modules
Bus matrix
CPU
DMA
RAM
DAC
OCD
USART
SPI
Timer /
Counter
TWI
USB
Interrupt
Controller
Power
Management
SRAM
External
Programming
External
Memory
EBI
PDI
AVR core
CH0
ADC
AC
Crypto
modules
Event System
Controller
Oscillator
Control
CH1
CH2
CH3
Non-Volatile
Memory
EEPROM
Flash
CRC
Real Time
Counter
I/O
NVM
Controller
Battery
Backup
