ATtiny15L
30
Timer/Counter1 in PWM mode
When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A – OCR1A form an 8-bit, free-run-
ning and glitch-free PWM with outputs on the PB1(OC1A) pin. Timer/Counter1 acts as an up-counter, counting up from $00
up to the value specified in the second output compare register OCR1B, and starting from $00 up again. When the counter
value matches the contents of the Output Compare register OCR1A, the PB1(OC1A) pin is set or cleared according to the
settings of the COM1A1/COM1A0 bits in the Timer/Counter1 Control Registers TCCR1. Refer to Table 12 for details.
Note that in PWM mode, writing to the Output Compare OCR1A, the data value, is first transferred to a temporary location.
The value is latched into OCR1A when the Timer/Counter reaches OCR1B. This prevents the occurrence of odd-length
PWM pulses (glitches) in the event of an unsynchronized OCR1A write. See Figure 22 for an example.
Figure 22.
Effects of Unsynchronized OCR Latching
During the time between the write and the latch operation, a read from OCR1A will read the contents of the temporary loca-
tion. This means that the most recently written value always will read out of OCR1A.
When OCR1A contains $00 or the top value, as specified in OCR1B register, the output PB1(OC1A) is held low or high
according to the settings of COM1A1/COM1A0. This is shown in Table 13.
Table 12.
Compare Mode Select in PWM Mode
COM1A1
COM1A0
Effect on Compare Pin
0
0
Not connected
0
1
Not connected
1
0
Cleared on compare match (upcounting) (non-inverted PWM). Set when TCNT1 = $00.
1
1
Set on compare match (upcounting) (inverted PWM). Cleared when TCNT1 = $00.
PWM Output OC1A
PWM Output OC1A
Unsynchronized OC1A Latch
Synchronized OC1A Latch
Counter Value
Compare Value
Counter Value
Compare Value
Compare Value changes
Glitch
Compare Value changes
