Atmel ATxmega128A1 Brochure & Specs Download

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picoPower Technology

Reducing power consumption—maintaining performance

picoPower — Best MCU power budget

Atmel’s picoPower technology reduces power
consumption in both sleep and active mode. With
picoPower technology the embedded designer
can reduce the applications power consumption
while maintaining performance.

True 1.6 Volt Operation

AVR XMEGA offers true 1.6 Volt operation. All functions including ADC, DAC, Flash- and EEPROM
memories are all operating down to 1.6V. This allows safe operation directly from a 1.8V ±10% power
supply. it also enables deeper battery discharge to increase battery life.

Minimized Leakage Current

AVR XMEGA leakage current is only 100 nA while still maintaining
full RAM and register retention. This reduces power consumption
for applications spending most time in sleep mode.

Ultra Low Power 32 kHz Crystal Oscillator

AVR XMEGA’s Real Time Counter consumes only 500 nA while
running from a 32.768 kHz Crystal Oscillator.

Sleep modes

XMEGA has five different sleep modes to turn off unused modules
and reduce the power consumption in the application. Many
sleep modes makes it easy to find the perfect fit for the applica-

tion. The granularity is further enhanced by the innovative Power Reduction Register technology.

in idle sleep mode all peripherals operate while the CPU is sleeping to reduce the power consumption. with
up to 50%, while event handling, communication and data input/output still run.

in power-save mode, XMEGA uses 650nA to run the Real Time Counter and have full SRAM and register
retention offering industry leading low power numbers. Enabling Watchdog and Brown Out adds only 1uA.

in power-down mode, XMEGA uses only 100nA with SRAM and register retetion, and 5us wake-up time
from pin change on any i/O pin and TWi address match.

Standby and extended standby sleep modes are identical to power-down and power-save, except the
external oscillator is kept running to reduce wake-up time.

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

ASYNC. CLK

MAIN CLK

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

Idle mode

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

ASYNC.

CLK.

MAIN

CLK.

BOD

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

BOD

CPU

I/O

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

ADC

ASYNC.

BOD

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

ASYNC.

CLK.

MAIN

CLK.

BOD

CPU

I/O

ADC

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

BOD

CPU

I/O

FLASH

WDT

T/C

CHANGE

INT.

DMA

EVENT

SYS.

TWI

SPI

USART

ADC

ASYNC.

BOD

Power-save mode

Power-down mode

Summary of Contents for ATxmega128A1

Page 1: ... AVR XMEGA 8 16 bit High Performance Low Power Flash Microcontrollers AVR MicrocontrolleRS ...

Page 2: ...MHz Event System and DMA controller High speed high resolution 12 bit ADC and DAC Crypto engine Timers Counters and fast communication interfaces Accurate and flexible Clock System with automatic clock failure protection AVR XMEGA Microcontollers Everywhere You Are tinyAVR megaAVR AVR XMEGA AP7 AVR32 UC3 AVR32 32 bit 8 16 bit 8 bit LESS POWER MORE PERFORMANCE Atmel is offering a wide range of AVR ...

Page 3: ...ve Power Reduction Register technology In idle sleep mode all peripherals operate while the CPU is sleeping to reduce the power consumption with up to 50 while event handling communication and data input output still run In power save mode XMEGA uses 650nA to run the Real Time Counter and have full SRAM and register retention offering industry leading low power numbers Enabling Watchdog and Brown ...

Page 4: ...e response time Up to 32 MIPS Single cycle execution Instruction set optimized for C 32x8 general purpose registers hardware multiplier Perfect for 8 16 bit applications Supports both AES and DES Reducing CPU time and power consumption Minimal CPU overhead for secure communication Off loads the CPU Saves power 4 channels Fast transfer between memories and peripherals 16 bit 32 bit cascaded Advance...

Page 5: ...terrupt Controller Internal 32 kHz 2 MHz 32 MHz PLL 1 accuracy External oscillator or clock input Dynamic and safe clock switching 1x 2048x prescaling Short wake up from sleep modes FAST and SECURE Up to 384 KB FLASH Up to 4 KB EEPROM Up to 32 KB SRAM 12 bit resolution 2 Msps ADC 1 Msps DAC Analog Comparator USART SPI Two Wire Interface I2C compatible External Bus Interface Debugging Programming ...

Page 6: ... send signals events directly to other peripherals without involving the CPU This ensures short and 100 predictable response time and at the same time offloads the CPU ALU 32 General Purpose Registers Central in the AVR architecture is the fast access register file with 32 x 8 bit general purpose working registers directly connected to the Arithmetic Logic Unit Within a single clock cycle the ALU ...

Page 7: ... XMEGA for crypto function do not limit where you can sell your product Analog and Digital Conversion CPU load at various communication speeds SPI kbps with DMA No DMA UART kbps with DMA No DMA 250 0 8 19 2 0 1 500 0 16 116 2 0 3 1 1 30 921 6 1 26 2 1 57 1 2 1 34 4 2 98 2 1 58 MSB without DMA with DMA 100 CPU usage Communication rate ADC 12 bit Compare Function VREF DAC TEMP SENSOR 8 16 External P...

Page 8: ...nal Clock Sources External Clock Sources High Frequency PLL Prescaler Block Reference clkCPU clkPER clkPER2 clkPER4 clkRTC High level Medium level Low level Program Flow and Interrupt execution 1 2 3 4 5 1 2 3 4 5 Main Main Main HOLD HOLD High level Medium level Program Flow and Interrupt execution 1 1 2 3 4 1 2 3 4 Main Main Main Medium level HOLD HOLD Input and Output AVR XMEGA offers flexible I...

Page 9: ...ices TWI The Two Wire Interface Bi directional 2 wire bus communication I2 C and SMBus compliant Slave operates in all Sleep Modes Full 100 kHz and 400 kHz support Master and Slave operation Normal mode of operation counting up or down CNT BOT MAX update PER CNT written DIRECTION CNT MAX New Period written to PERBUF that is higher than current CNT New Period written to PERBUF that is lower than cu...

Page 10: ...real time access to all peripheral registers data and program memories and support unlimited number of break points XMEGA has a fast serial programming interface for production line or in system programming Using a bootloader XMEGA can receive flash upgrades in the field through any interface without reset or halt of critical program execution The crypto engine and a serial number in each device e...

Page 11: ...D3 F 64 4 2 4 4 50 5 18 Y 2 1 3 1x16 2 67 50 1 6 3 6 32 TQFP64 QFN64 ATxmega128D3 F 128 8 2 8 4 50 5 18 Y 2 1 3 1x16 2 67 50 1 6 3 6 32 TQFP64 QFN64 ATxmega192D3 F 192 8 2 16 4 50 5 18 Y 2 1 3 1x16 2 67 50 1 6 3 6 32 TQFP64 QFN64 ATxmega256D3 F 256 8 4 16 4 50 5 18 Y 2 1 3 1x16 2 67 50 1 6 3 6 32 TQFP64 QFN64 ATxmega16D4 F 16 4 1 2 4 34 4 14 Y 2 1 2 1x12 2 55 34 1 6 3 6 32 TQFP44 QFN44 ATxmega32D4...

Page 12: ... of Atmel products EXCEPT AS SET FORTH IN ATMEL S TERMS AND CONDITIONS OF SALES LOCATED ON ATMEL S WEB SITE ATMEL ASSUMES NO LIABILITY WHAT SOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT I...

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