Atmel ATSAML22G16A-AUT, Manual

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• The type of CRC calculation must be selected by writing the CRC Polynomial Type bit group in the
CRC Control register (CRCCTRL.CRCPOLY)
• If I/O is selected as input source, the beat size must be selected by writing the CRC Beat Size bit
group in the CRC Control register (CRCCTRL.CRCBEATSIZE)
26.6.2.2. Enabling, Disabling, and Resetting
The DMAC is enabled by writing the DMA Enable bit in the Control register ( CTRL .DMAENABLE) to '1'.
The DMAC is disabled by writing a '0' to CTRL .DMAENABLE.
A DMA channel is enabled by writing the Enable bit in the Channel Control A register
(
CHCTRLA .ENABLE) to '1', after writing the corresponding channel id to the Channel ID bit group in the
Channel ID register ( CHID .ID). A DMA channel is disabled by writing a '0' to CHCTRLA .ENABLE.
The CRC is enabled by writing a '1' to the CRC Enable bit in the Control register ( CTRL .CRCENABLE).
The CRC is disabled by writing a '0' to CTRL .CRCENABLE.
The DMAC is reset by writing a '1' to the Software Reset bit in the Control register ( CTRL .SWRST) while
the DMAC and CRC are disabled. All registers in the DMAC except DBGCTRL will be reset to their initial
state.
A DMA channel is reset by writing a '1' to the Software Reset bit in the Channel Control A register
(
CHCTRLA .SWRST), after writing the corresponding channel id to the Channel ID bit group in the
Channel ID register ( CHID .ID). The channel registers will be reset to their initial state. The corresponding
DMA channel must be disabled in order for the reset to take effect.
26.6.2.3. Transfer Descriptors
Together with the channel configurations the transfer descriptors decides how a block transfer should be
executed. Before a DMA channel is enabled (
CHCTRLA .ENABLE is written to one), and receives a
transfer trigger, its first transfer descriptor has to be initialized and valid ( BTCTRL .VALID). The first
transfer descriptor describes the first block transfer of a transaction.
All transfer descriptors must reside in SRAM. The addresses stored in the Descriptor Memory Section
Base Address (
BASEADDR ) and Write-Back Memory Section Base Address ( WRBADDR ) registers tell
the DMAC where to find the descriptor memory section and the write-back memory section.
The descriptor memory section is where the DMAC expects to find the first transfer descriptors for all
DMA channels. As
BASEADDR points only to the first transfer descriptor of channel 0 (see figure below),
all first transfer descriptors must be stored in a contiguous memory section, where the transfer descriptors
must be ordered according to their channel number. For further details on linked descriptors, refer to
Linked Descriptors .
The write-back memory section is the section where the DMAC stores the transfer descriptors for the
ongoing block transfers.
WRBADDR points to the ongoing transfer descriptor of channel 0. All ongoing
transfer descriptors will be stored in a contiguous memory section where the transfer descriptors are
ordered according to their channel number. The figure below shows an example of linked descriptors on
DMA channel 0. For further details on linked descriptors, refer to
Linked Descriptors .
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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