26.8.18. Channel Control A
This register affects the DMA channel that is selected in the Channel ID register (CHID.ID).
Name:
CHCTRLA
Offset:
0x40
Reset:
0x00
Property:
PAC Write-Protection, Enable-Protected
Bit
7
6
5
4
3
2
1
0
RUNSTDBY
ENABLE
SWRST
Access
R/W
R/W
R/W
Reset
0
0
0
Bit 6 – RUNSTDBY: Channel run in standby
This bit is used to keep the DMAC channel running in standby mode.
This bit is not enable-protected.
Value
Description
0
The DMAC channel is halted in standby.
1
The DMAC channel continues to run in standby.
Bit 1 – ENABLE: Channel Enable
Writing a '0' to this bit during an ongoing transfer, the bit will not be cleared until the internal data transfer
buffer is empty and the DMA transfer is aborted. The internal data transfer buffer will be empty once the
ongoing burst transfer is completed.
Writing a '1' to this bit will enable the DMA channel.
This bit is not enable-protected.
Value
Description
0
DMA channel is disabled.
1
DMA channel is enabled.
Bit 0 – SWRST: Channel Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit resets the channel registers to their initial state. The bit can be set when the
channel is disabled (ENABLE=0). Writing a '1' to this bit will be ignored as long as ENABLE=1. This bit is
automatically cleared when the reset is completed.
Value
Description
0
There is no reset operation ongoing.
1
The reset operation is ongoing.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
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