26.8.1. Control
Name:
CTRL
Offset:
0x00
Reset:
0x00X0
Property:
PAC Write-Protection, Enable-Protected
Bit
15
14
13
12
11
10
9
8
LVLEN3
LVLEN2
LVLEN1
LVLEN0
Access
R/W
R/W
R/W
R/W
Reset
0
0
0
0
Bit
7
6
5
4
3
2
1
0
CRCENABLE
DMAENABLE
SWRST
Access
R/W
R/W
R/W
Reset
0
0
0
Bit 2 – CRCENABLE: CRC Enable
Writing a '0' to this bit will disable the CRC calculation when the CRC Status Busy flag is cleared
(CRCSTATUS. CRCBUSY). The bit is zero when the CRC is disabled.
Writing a '1' to this bit will enable the CRC calculation.
Value
Description
0
The CRC calculation is disabled.
1
The CRC calculation is enabled.
Bit 1 – DMAENABLE: DMA Enable
Setting this bit will enable the DMA module.
Writing a '0' to this bit will disable the DMA module. When writing a '0' during an ongoing transfer, the bit
will not be cleared until the internal data transfer buffer is empty and the DMA transfer is aborted. The
internal data transfer buffer will be empty once the ongoing burst transfer is completed.
This bit is not enable-protected.
Value
Description
0
The peripheral is disabled.
1
The peripheral is enabled.
Bit 0 – SWRST: Software Reset
Writing a '0' to this bit has no effect.
Writing a '1' to this bit when both the DMAC and the CRC module are disabled (DMAENABLE and
CRCENABLE are '0') resets all registers in the DMAC (except DBGCTRL) to their initial state. If either the
DMAC or CRC module is enabled, the Reset request will be ignored and the DMAC will return an access
error.
Atmel SAM L22G / L22J / L22N [DATASHEET]
Atmel-42402E-SAM L22G / L22J / L22N_Datasheet_Complete-07/2016
457
