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ATmega8535(L)

2502K–AVR–10/06

The ADC module contains a prescaler, which generates an acceptable ADC clock fre-
quency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits
in ADCSRA. The prescaler starts counting from the moment the ADC is switched on by
setting the ADEN bit in ADCSRA. The prescaler keeps running for as long as the ADEN
bit is set, and is continuously reset when ADEN is low.

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the con-
version starts at the following rising edge of the ADC clock cycle. See “Differential Gain
Channels” on page 212 for details on differential conversion timing.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal
conversion and 13.5 ADC clock cycles after the start of an first conversion. When a con-
version is complete, the result is written to the ADC Data Registers, and ADIF is set. In
Single Conversion mode, ADSC is cleared simultaneously. The software may then set
ADSC again, and a new conversion will be initiated on the first rising ADC clock edge.

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the
sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger
source signal. Three additional CPU clock cycles are used for synchronization logic.

In Free Running mode, a new conversion will be started immediately after the conver-
sion completes, while ADSC remains high. For a summary of conversion times, see
Table 82.

Figure 101.

ADC Timing Diagram, First Conversion (Single Conversion Mode)

MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

First Conversion

Next
Conversion

3

MUX and REFS
Update

MUX and REFS
Update

Conversion

Complete

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Summary of Contents for ATmega8535

Page 1: ...e Real Time Counter with Separate Oscillator Four PWM Channels 8 channel 10 bit ADC 8 Single ended Channels 7 Differential Channels for TQFP Package Only 2 Differential Channels with Programmable Gain at 1x 10x or 200x for TQFP Package Only Byte oriented Two wire Serial Interface Programmable Serial USART Master Slave SPI Serial Interface Programmable Watchdog Timer with Separate On chip Oscillato...

Page 2: ...OSI PB5 MISO PB6 SCK PB7 RESET VCC GND XTAL2 XTAL1 RXD PD0 TXD PD1 INT0 PD2 PA4 ADC4 PA5 ADC5 PA6 ADC6 PA7 ADC7 AREF GND AVCC PC7 TOSC2 PC6 TOSC1 PC5 PC4 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 INT1 PD3 OC1B PD4 OC1A PD5 ICP1 PD6 OC2 PD7 VCC GND SCL PC0 SDA PC1 PC2 PC3 PB4 SS PB3 AIN1 OC0 PB2 AIN0 INT2 PB1 T1 PB0 XCK T0 GND VCC PA0 ADC0 PA1 ADC1 PA2 ADC2 PA3 ADC3 7 8 9 10...

Page 3: ...LATOR WATCHDOG TIMER MCU CTRL TIMING OSCILLATOR TIMERS COUNTERS INTERRUPT UNIT STACK POINTER EEPROM SRAM STATUS REGISTER USART PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER PROGRAMMING LOGIC SPI ADC INTERFACE COMP INTERFACE PORTA DRIVERS BUFFERS PORTA DIGITAL INTERFACE GENERAL PURPOSE REGISTERS X Y Z ALU PORTC DRIVERS BUFFERS PORTC DIGITAL INTERFACE PORTB DIGITAL INTERFACE...

Page 4: ... Oscillator and the asynchro nous timer continue to run The device is manufactured using Atmel s high density nonvolatile memory technology The On chip ISP Flash allows the program memory to be reprogrammed In System through an SPI serial interface by a conventional nonvolatile memory programmer or by an On chip Boot program running on the AVR core The boot program can use any interface to downloa...

Page 5: ... C output buffers have symmetrical drive characteristics with both high sink and source capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running Port D PD7 PD0 Port D is an 8 bit bi directional I O port with internal pull up resisto...

Page 6: ...6 ATmega8535 L 2502K AVR 10 06 Resources A comprehensive set of development tools application notes and datasheets are avail able for download on http www atmel com avr ...

Page 7: ...use various parts of the device These code examples assume that the part specific header file is included before compilation Be aware that not all C compiler vendors include bit defini tions in the header files and interrupt handling in C is compiler dependent Please confirm with the C Compiler documentation for more details ...

Page 8: ...ction is pre fetched from the program memory This concept enables instructions to be executed in every clock cycle The program memory is In System Re Programmable Flash memory The fast access Register File contains 32 x 8 bit general purpose working registers with a single clock cycle access time This allows single cycle Arithmetic Logic Unit ALU operation In a typical ALU operation two operands a...

Page 9: ...he Stack size is only limited by the total SRAM size and the usage of the SRAM All user programs must initialize the SP in the reset routine before subroutines or interrupts are executed The Stack Pointer SP is read write accessible in the I O space The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture The memory spaces in the AVR archit...

Page 10: ...on set reference Bit 6 T Bit Copy Storage The Bit Copy instructions BLD Bit LoaD and BST Bit STore use the T bit as source or destination for the operated bit A bit from a register in the Register file can be copied into T by the BST instruction and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction Bit 5 H Half Carry Flag The Half Carry Flag H indicates ...

Page 11: ... Registers Most of the instructions operating on the Register File have direct access to all registers and most of them are single cycle instructions As shown in Figure 4 each register is also assigned a data memory address mapping them directly into the first 32 locations of the user Data Space Although not being phys ically implemented as SRAM locations this memory organization provides great fl...

Page 12: ...pace in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled The Stack Pointer must be set to point above 0x60 The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt The Stack Pointer...

Page 13: ...m memory space All interrupts are assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Register in order to enable the interrupt Depending on the Program Counter value interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed This feature improves software security See the section Memory Program...

Page 14: ...leared the cor responding interrupt flag s will be set and remembered until the Global Interrupt Enable bit is set and will then be executed by order of priority The second type of interrupts will trigger as long as the interrupt condition is present These interrupts do not necessarily have interrupt flags If the interrupt condition disap pears before the interrupt is enabled the interrupt will no...

Page 15: ...ecution of a multi cycle instruction this instruction is completed before the interrupt is served If an interrupt occurs when the MCU is in sleep mode the interrupt execution response time is increased by four clock cycles This increase comes in addition to the start up time from the selected sleep mode A return from an interrupt handling routine takes four clock cycles During these four clock cyc...

Page 16: ...Program section and Application Program section The Flash memory has an endurance of at least 10 000 write erase cycles The ATmega8535 Program Counter PC is 12 bits wide thus addressing the 4K program memory locations The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in Boot Loader Support Read While Write Self Programming on page 2...

Page 17: ...isters The direct addressing reaches the entire data space The Indirect with Displacement mode reaches 63 address locations from the base address given by the Y or Z register When using register indirect addressing modes with automatic pre decrement and post increment the address registers X Y and Z are decremented or incremented The 32 general purpose working registers 64 I O Registers and the 51...

Page 18: ... space The write access time for the EEPROM is given in Table 1 A self timing function how ever lets the user software detect when the next byte can be written If the user code contains instructions that write the EEPROM some precautions must be taken In heavily filtered power supplies VCC is likely to rise or fall slowly on Power up down This causes the device for some period of time to run at a ...

Page 19: ... the I bit in SREG is set Writing EERIE to zero disables the interrupt The EEPROM Ready interrupt generates a constant interrupt when EEWE is cleared Bit 2 EEMWE EEPROM Master Write Enable The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written When EEMWE is set setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero...

Page 20: ...terrupting another EEPROM access the EEAR or EEDR Register will be modified causing the interrupted EEPROM access to fail It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems When the write access time has elapsed the EEWE bit is cleared by hardware The user software can poll this bit and wait for a zero before writing the next byte When EEWE has...

Page 21: ...ny ongoing SPM com mand to finish Assembly Code Example EEPROM_write Wait for completion of previous write sbic EECR EEWE rjmp EEPROM_write Set up address r18 r17 in address register out EEARH r18 out EEARL r17 Write data r16 to Data Register out EEDR r16 Write logical one to EEMWE sbi EECR EEMWE Start eeprom write by setting EEWE sbi EECR EEWE ret C Code Example void EEPROM_write unsigned int uiA...

Page 22: ...d because the supply volt age is too low for the CPU and the EEPROM to operate properly These issues are the same as for board level systems using EEPROM and the same design solutions should be applied An EEPROM data corruption can be caused by two situations when the voltage is too low First a regular write sequence to the EEPROM requires a minimum voltage to operate correctly Secondly the CPU it...

Page 23: ...working registers and the I O space I O Registers within the address range 0x00 0x1F are directly bit accessible using the SBI and CBI instructions In these registers the value of single bits can be checked by using the SBIS and SBIC instructions Refer to the instruction set section for more details When using the I O specific commands IN and OUT the I O addresses 0x00 0x3F must be used When addre...

Page 24: ...ulations I O Clock clkI O The I O clock is used by the majority of the I O modules like Timer Counters SPI and USART The I O clock is also used by the External Interrupt module but note that some external interrupts are detected by asynchronous logic allowing such interrupts to be detected even if the I O clock is halted Also note that address recognition in the TWI module is carried out asynchron...

Page 25: ...ach time out is shown in Table 3 The frequency of the Watchdog Oscil lator is voltage dependent as shown in ATmega8535 Typical Characteristics on page 266 Default Clock Source The device is shipped with CKSEL 0001 and SUT 10 The default clock source setting is therefore the Internal RC Oscillator with longest startup time This default set ting ensures that all users can make their desired clock so...

Page 26: ...osing capacitors for use with crystals are given in Table 4 For ceramic resonators the capacitor values given by the manufacturer should be used Figure 12 Crystal Oscillator Connections The Oscillator can operate in three different modes each optimized for a specific fre quency range The operating mode is selected by the fuses CKSEL3 1 as shown in Table 4 2 This option should not be used with crys...

Page 27: ...ose to the maximum frequency of the device and if frequency stability at start up is not important for the application Table 5 Start up Times for the Crystal Oscillator Clock Selection CKSEL0 SUT1 0 Start up Time from Power down and Power save Additional Delay from Reset VCC 5 0V Recommended Usage 0 00 258 CK 1 4 1 ms Ceramic resonator fast rising power 0 01 258 CK 1 65 ms Ceramic resonator slowly...

Page 28: ...on shown in Figure 13 can be used The frequency is roughly estimated by the equation f 1 3RC C should be at least 22 pF By programming the CKOPT Fuse the user can enable an internal 36 pF capacitor between XTAL1 and GND thereby removing the need for an external capacitor For more information on Oscillator operation and details on how to choose R and C refer to the External RC Oscillator applicatio...

Page 29: ...lication notes available at www atmel com avr it is possible to achieve 1 accuracy at any given VCC and Temperature When this Oscillator is used as the chip clock the Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time out For more information on the pre programmed calibration value see the section Calibration Byte on page 239 Note 1 The device is shipped with this...

Page 30: ...ncy of the Internal Oscillator Writing 0xFF to the register gives the highest available frequency The calibrated Oscillator is used to time EEPROM and Flash access If EEPROM or Flash is written do not calibrate to more than 10 above the nominal frequency Otherwise the EEPROM or Flash write may fail Note that the Oscillator is intended for calibration to 1 0 2 0 4 0 or 8 0 MHz Tuning to other value...

Page 31: ...MCU A variation in frequency of more than 2 from one clock cycle to the next can lead to unpredictable behavior It is required to ensure that the MCU is kept in Reset during such changes in the clock frequency Timer Counter Oscillator For AVR microcontrollers with Timer Counter Oscillator pins TOSC1 and TOSC2 the crystal is connected directly between the pins No external capacitors are needed The ...

Page 32: ...and executes from the Reset Vector Figure 11 on page 24 presents the different clock systems in the ATmega8535 and their distribution The figure is helpful in selecting an appropriate sleep mode MCU Control Register MCUCR The MCU Control Register contains control bits for power management Bits 7 5 4 SM2 0 Sleep Mode Select Bits 2 1 and 0 These bits select between the six available sleep modes as s...

Page 33: ...n INT0 or INT1 or an external interrupt on INT2 can wake up the MCU from ADC Noise Reduction mode Power down Mode When the SM2 0 bits are written to 010 the SLEEP instruction makes the MCU enter Power down mode In this mode the External Oscillator is stopped while the External Interrupts the Two wire Serial Interface address watch and the Watchdog continue operating if enabled Only an External Res...

Page 34: ...resonator clock option is selected the SLEEP instruction makes the MCU enter Extended Standby mode This mode is identical to Power save mode with the exception that the Oscillator is kept running From Extended Standby mode the device wakes up in six clock cycles Notes 1 External Crystal or resonator selected as clock source 2 If AS2 bit in ASSR is set 3 Only INT2 or level interrupt INT1 and INT0 T...

Page 35: ...eper sleep modes this will contribute significantly to the total current consumption Refer to Brown out Detection on page 39 for details on how to configure the Brown out Detector Internal Voltage Reference The Internal Voltage Reference will be enabled when needed by the Brown out Detec tor the Analog Comparator or the ADC If these modules are disabled as described in the sections above the inter...

Page 36: ...l state when a reset source goes active This does not require any clock source to be running After all reset sources have gone inactive a delay counter is invoked stretching the internal reset This allows the power to reach a stable level before normal operation starts The time out period of the delay counter is defined by the user through the CKSEL Fuses The different selections for the delay per...

Page 37: ... RESET Pin Threshold Voltage 0 2 0 9 V tRST Minimum pulse width on RESET Pin 1 5 µs VBOT Brown out Reset Threshold Voltage 3 BODLEVEL 1 2 5 2 7 2 9 V BODLEVEL 0 3 6 4 0 4 2 tBOD Minimum low voltage period for Brown out Detection BODLEVEL 1 2 µs BODLEVEL 0 2 µs VHYST Brown out Detector hysteresis 130 mV MCU Control and Status Register MCUCSR Brown out Reset Circuit BODEN BODLEVEL Delay Counters CKS...

Page 38: ...n chip detection circuit The detec tion level is defined in Table 15 The POR is activated whenever VCC is below the detection level The POR circuit can be used to trigger the Start up Reset as well as to detect a failure in supply voltage A Power on Reset POR circuit ensures that the device is reset from Power on Reach ing the Power on Reset threshold voltage invokes the delay counter which determ...

Page 39: ... for the BOD can be selected by the fuse BODLEVEL to be 2 7V BODLEVEL unprogrammed or 4 0V BODLEVEL programmed The trigger level has a hysteresis to ensure spike free Brown out Detection The hysteresis on the detection level should be interpreted as VBOT VBOT VHYST 2 and VBOT VBOT VHYST 2 The BOD circuit can be enabled disabled by the fuse BODEN When the BOD is enabled BODEN programmed and VCC dec...

Page 40: ...ORF Brown out Reset Flag This bit is set if a Brown out Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 1 EXTRF External Reset Flag This bit is set if an External Reset occurs The bit is reset by a Power on Reset or by writing a logic zero to the flag Bit 0 PORF Power on Reset Flag This bit is set if a Power on Reset occurs The bit is reset only by writ...

Page 41: ...ower down mode Note 1 Values are guidelines only Watchdog Timer The Watchdog Timer is clocked from a separate On chip Oscillator which runs at 1 MHz This is the typical value at VCC 5V See characterization data for typical values at other VCC levels By controlling the Watchdog Timer prescaler the Watchdog Reset interval can be adjusted as shown in Table 18 on page 43 The WDR Watchdog Reset instruc...

Page 42: ...onfiguration of the Watchdog Timer on page 45 Bit 3 WDE Watchdog Enable When the WDE is written to logic one the Watchdog Timer is enabled and if the WDE is written to logic zero the Watchdog Timer function is disabled WDE can only be cleared Table 17 WDT Configuration as a Function of the Fuse Settings of S8538C and WDTON S8535C WDTON Safety Level WDTInitial State How to Disable the WDT How to Ch...

Page 43: ...uration of the Watchdog Timer on page 45 Bits 2 0 WDP2 WDP1 WDP0 Watchdog Timer Prescaler 2 1 and 0 The WDP2 WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled The different prescaling values and their corresponding Timeout Periods are shown in Table 18 Note 1 Values are guidelines only Table 18 Watchdog Timer Prescale Select 1 WDP2 WDP1 WDP0 Number of WD...

Page 44: ...ng interrupts globally so that no interrupts will occur during execution of these functions Assembly Code Example WDT_off Reset WDT wdr Write logical one to WDCE and WDE in r16 WDTCR ori r16 1 WDCE 1 WDE out WDTCR r16 Turn off WDT ldi r16 0 WDE out WDTCR r16 ret C Code Example void WDT_off void Reset WDT _WDR Write logical one to WDCE and WDE WDTCR 1 WDCE 1 WDE Turn off WDT WDTCR 0x00 ...

Page 45: ...er is initially disabled but can be enabled by writing the WDE bit to 1 without any restriction A timed sequence is needed when changing the Watchdog Time out period or disabling an enabled Watchdog Timer To disable an enabled Watchdog Timer and or changing the Watchdog Time out the following proce dure must be followed 1 In the same operation write a logic one to WDCE and WDE A logic one must be ...

Page 46: ... case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa Table 19 Reset and Interrupt Vectors Vector No Program Address 2 Source Interrupt Definition 1 0x000 1 RESET External Pin Power on Reset Brown out Reset and Watchdog Reset 2 0x001 INT0 External Interrupt Request 0 3 0x002 INT1 External Interrupt Request 1 4 0x003 TIMER2 COMP Ti...

Page 47: ...er 0x00D rjmp USART_TXC USART TX Complete Handler 0x00E rjmp ADC ADC Conversion Complete Handler 0x00F rjmp EE_RDY EEPROM Ready Handler 0x010 rjmp ANA_COMP Analog Comparator Handler 0x011 rjmp TWSI Two wire Serial Interface Handler 0x012 rjmp EXT_INT2 IRQ2 Handler 0x013 rjmp TIM0_COMP Timer0 Compare Handler 0x014 rjmp SPM_RDY Store Program Memory Ready Handler 0x015 RESET ldi r16 high RAMEND Main ...

Page 48: ...p SPM_RDY Store Program Memory Ready Handler org 0xC00 0xC00RESET ldi r16 high RAMEND Main program start 0xC01 out SPH r16 Set Stack Pointer to top of RAM 0xC02 ldi r16 low RAMEND 0xC03 out SPL r16 0xC04 sei Enable interrupts 0xC05 instr xxx When the BOOTRST Fuse is programmed the Boot section size set to 2K bytes and the IVSEL bit in the GICR Register is set before any interrupts are enabled the ...

Page 49: ... sequence is executed Interrupts are disabled in the cycle IVCE is set and they remain disabled until after the instruction fol lowing the write to IVSEL If IVSEL is not written interrupts remain disabled for four cycles The I bit in the Status Register is unaffected by the automatic disabling Note If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro grammed in...

Page 50: ...Enable change of interrupt vectors ldi r16 1 IVCE out GICR r16 Move interrupts to boot Flash section ldi r16 1 IVSEL out GICR r16 ret C Code Example void Move_interrupts void Enable change of interrupt vectors GICR 1 IVCE Move interrupts to boot Flash section GICR 1 IVSEL ...

Page 51: ...s the bit number However when using the register or bit defines in a program the precise form must be used For example PORTB3 for bit no 3 in Port B here documented generally as PORTxn The physical I O Registers and bit locations are listed in Register Descrip tion for I O Ports on page 66 Three I O memory address locations are allocated for each port one each for the Data Register PORTx Data Dire...

Page 52: ...ogic zero Pxn is config ured as an input pin If PORTxn is written a logic one when the pin is configured as an input pin the pull up resistor is activated To switch the pull up resistor off PORTxn has to be written logic zero or the pin has to be configured as an output pin The port pins are tri stated when a reset condition becomes active even if no clocks are running If PORTxn is written a logic...

Page 53: ...ility if the physical pin changes value near the edge of the internal clock but it also introduces a delay Figure 24 shows a timing diagram of the synchronization when reading an externally applied pin value The maximum and minimum propagation delays are denoted tpd max and tpd min respectively Figure 24 Synchronization when Reading an Externally Applied Pin Value Consider the clock period startin...

Page 54: ... When reading back a software assigned pin value a nop instruction must be inserted as indicated in Figure 25 The out instruction sets the SYNC LATCH signal at the positive edge of the clock In this case the delay tpd through the synchronizer is one system clock period Figure 25 Synchronization when Reading a Software Assigned Pin Value out PORTx r16 nop in r17 PINx 0xFF 0x00 0xFF SYSTEM CLK r16 I...

Page 55: ...mode to avoid high power consumption if some input signals are left floating or have an analog signal level close to VCC 2 SLEEP is overridden for port pins enabled as External Interrupt pins If the External Interrupt Request is not enabled SLEEP is active also for these pins SLEEP is also overridden by various other alternate functions as described in Alternate Port Func tions on page 57 If a log...

Page 56: ...ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled Reset Active mode and Idle mode The simplest method to ensure a defined level of an unused pin is to enable the internal pull up In this case the pull up will be disabled during reset If low power consumption during reset is important it is recommended to use an external pull up or pu...

Page 57: ...ignals are unique for each pin clk RPx RRx WPx RDx WDx PUD SYNCHRONIZER WDx WRITE DDRx WPx WRITE PORTx RRx READ PORTx REGISTER RPx READ PORTx PIN PUD PULLUP DISABLE clkI O I O CLOCK RDx READ DDRx D L Q Q SET CLR 0 1 0 1 0 1 DIxn AIOxn DIEOExn PVOVxn PVOExn DDOVxn DDOExn PUOExn PUOVxn PUOExn Pxn PULL UP OVERRIDE ENABLE PUOVxn Pxn PULL UP OVERRIDE VALUE DDOExn Pxn DATA DIRECTION OVERRIDE ENABLE DDOV...

Page 58: ...alue If DDOE is set the Output Driver is enabled disabled when DDOV is set cleared regardless of the setting of the DDxn Register bit PVOE Port Value Override Enable If this signal is set and the Output Driver is enabled the port value is controlled by the PVOV signal If PVOE is cleared and the Output Driver is enabled the port Value is controlled by the PORTxn Register bit PVOV Port Value Overrid...

Page 59: ...e 24 and Table 25 relate the alternate functions of Port A to the overriding signals shown in Figure 26 on page 57 Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 ACME PUD PSR2 PSR10 SFIOR Read Write R W R W R W R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table 23 Port A Pins Alternate Functions Port Pin Alternate Function PA7 ADC7 ADC input channel 7 PA6 ADC6 ADC input channel 6 PA5 ADC5 ADC input chan...

Page 60: ...enabled as a Slave the data direction of this pin is controlled by DDB6 When the pin is forced by the SPI to be an input the pull up can still be con trolled by the PORTB6 bit Table 25 Overriding Signals for Alternate Functions in PA3 PA0 Signal Name PA3 ADC3 PA2 ADC2 PA1 ADC1 PA0 ADC0 PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI AIO ...

Page 61: ...rfering with the function of the Analog Comparator OC0 Output Compare Match output The PB3 pin can serve as an external output for the Timer Counter0 Compare Match The PB3 pin has to be configured as an output DDB3 set one to serve this function The OC0 pin is also the output pin for the PWM mode timer function AIN0 INT2 Port B Bit 2 AIN0 Analog Comparator Positive input Configure the port pin as ...

Page 62: ... SCK OUTPUT SPI SLAVE OUTPUT SPI MSTR OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI SCK INPUT SPI MSTR INPUT SPI SLAVE INPUT SPI SS AIO Table 28 Overriding Signals for Alternate Functions in PB3 PB0 Signal Name PB3 OC0 AIN1 PB2 INT2 AIN0 PB1 T1 PB0 T0 XCK PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC0 ENABLE 0 0 UMSEL PVOV OC0 0 0 XCK OUTPUT DIEOE 0 INT2 ENABLE 0 0 DIEOV 0 1 0 0 DI INT2 IN...

Page 63: ...ere is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal and the pin is driven by an open drain driver with slew rate limitation When this pin is used by the Two wire Serial Interface the pull up can still be controlled by the PORTC1 bit SCL Port C Bit 0 SCL Two wire Serial Interface Clock When the TWEN bit in TWCR is set one to enable the Two wire Serial Interfac...

Page 64: ...function ICP1 Port D Bit 6 ICP1 Input Capture Pin The PD6 pin can act as an Input Capture pin for Timer Counter1 OC1A Port D Bit 5 OC1A Output Compare Match A output The PD5 pin can serve as an external output for the Timer Counter1 Output Compare A The pin has to be configured as an output Table 31 Overriding Signals for Alternate Functions in PC1 PC0 1 Signal Name PC1 SDA PC0 SCL PUOE TWEN TWEN ...

Page 65: ...rce TXD Port D Bit 1 TXD Transmit Data Data output pin for the USART When the USART Transmitter is enabled this pin is configured as an output regardless of the value of DDD1 RXD Port D Bit 0 RXD Receive Data Data input pin for the USART When the USART Receiver is enabled this pin is configured as an input regardless of the value of DDD0 When the USART forces this pin to be an input the pull up ca...

Page 66: ...6 5 4 3 2 1 0 PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read Write R R R R R R R R Initial Value...

Page 67: ...0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read Write R W R W R W R W R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 0 PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC Read Write R R R R R R R R Initial Value N A N A N A N A N A N A N A N A Bit 7 6 5 4 3 2 1 0 PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD Read Write R W R W...

Page 68: ...e input has the required level during this sampling or if it is held until the end of the start up time The start up time is defined by the SUT Fuses as described in System Clock and Clock Options on page 24 If the level is sampled twice by the Watchdog Oscillator clock but disappears before the end of the start up time the MCU will still wake up but no interrupt will be generated The required lev...

Page 69: ...t disable INT2 by clearing its Interrupt Enable bit in the GICR Register Then the ISC2 bit can be changed Finally the INT2 Interrupt Flag should be cleared by writing a logical one to its Interrupt Flag bit INTF2 in the GIFR Register before the interrupt is re enabled General Interrupt Control Register GICR Bit 7 INT1 External Interrupt Request 1 Enable When the INT1 bit is set one and the I bit i...

Page 70: ...T1 pin triggers an interrupt request INTF1 becomes set one If the I bit in SREG and the INT1 bit in GICR are set one the MCU will jump to the corresponding Interrupt Vector The flag is cleared when the interrupt routine is executed Alternatively the flag can be cleared by writing a logical one to it This flag is always cleared when INT1 is configured as a level interrupt Bit 6 INTF0 External Inter...

Page 71: ...mer Counter Block Diagram Registers The Timer Counter TCNT0 and Output Compare Register OCR0 are 8 bit registers Interrupt request abbreviated to Int Req in the figure signals are all visible in the Timer Interrupt Flag Register TIFR All interrupts are individually masked with the Timer Interrupt Mask Register TIMSK TIFR and TIMSK are not shown in the figure since these registers are shared by oth...

Page 72: ... Select logic which is controlled by the clock select CS02 0 bits located in the Timer Counter Control Register TCCR0 For details on clock sources and prescaler see Timer Counter0 and Timer Counter1 Prescalers on page 87 Counter Unit The main part of the 8 bit Timer Counter is the programmable bi directional counter unit Figure 28 shows a block diagram of the counter and its surroundings Figure 28...

Page 73: ...ag TOV0 is set according to the mode of operation selected by the WGM01 0 bits TOV0 can be used for generating a CPU interrupt Output Compare Unit The 8 bit comparator continuously compares TCNT0 with the Output Compare Register OCR0 Whenever TCNT0 equals OCR0 the comparator signals a match A match will set the Output Compare Flag OCF0 at the next timer clock cycle If enabled OCIE0 1 and Global In...

Page 74: ...toggled Compare Match Blocking by TCNT0 Write All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle even when the timer is stopped This feature allows OCR0 to be initialized to the same value as TCNT0 without triggering an interrupt when the Timer Counter clock is enabled Using the Output Compare Unit Since writing TCNT0 in any mode of...

Page 75: ...the port pin The Data Direction Register bit for the OC0 pin DDR_OC0 must be set as output before the OC0 value is visible on the pin The port override function is independent of the Waveform Generation mode The design of the output compare pin logic allows initialization of the OC0 state before the output is enabled Note that some COM01 0 bit settings are reserved for certain modes of operation S...

Page 76: ...y set not cleared However combined with the Timer Overflow interrupt that automatically clears the TOV0 Flag the timer resolution can be increased by software There are no special cases to consider in the normal mode a new counter value can be written anytime The output compare unit can be used to generate interrupts at some given time Using the output compare to generate waveforms in Normal mode ...

Page 77: ... WGM01 0 3 provides a high fre quency PWM waveform generation option The fast PWM differs from the other PWM option by its single slope operation The counter counts from BOTTOM to MAX then restarts from BOTTOM In non inverting Compare Output mode the Output Compare OC0 is cleared on the Compare Match between TCNT0 and OCR0 and set at BOT TOM In inverting Compare Output mode the output is set on Co...

Page 78: ...e PWM frequency for the output can be calculated by the following equation The N variable represents the prescale factor 1 8 64 256 or 1024 The extreme values for the OCR0 Register represents special cases when generating a PWM waveform output in the fast PWM mode If the OCR0 is set equal to BOTTOM the output will be a narrow spike for each MAX 1 timer clock cycle Setting the OCR0 equal to MAX wil...

Page 79: ... timing diagram for the phase correct PWM mode is shown on Figure 33 The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT0 slopes repre sent compare matches between OCR0 and TCNT0 Figure 33 Phase Correct PWM Mode Timing Diagram The Timer Counter ...

Page 80: ... OCR0 changes its value from MAX like in Figure 33 When the OCR0 value is MAX the OCn pin value is the same as the result of a down counting Compare Match To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up counting Compare Match The timer starts counting from a value higher than the one in OCR0 and for that reason misses the Compare Match and hence the OCn...

Page 81: ... of OCF0 in all modes except CTC mode Figure 36 Timer Counter Timing Diagram Setting of OCF0 with Prescaler fclk_I O 8 Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode TOVn TCNTn MAX 1 MAX BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 OCFn OCRn TCNTn OCRn Value OCRn 1 OCRn OCRn 1 OCRn 2 clkI O clkTn clkI O 8 ...

Page 82: ...82 ATmega8535 L 2502K AVR 10 06 Figure 37 Timer Counter Timing Diagram Clear Timer on Compare Match Mode with Prescaler fclk_I O 8 OCFn OCRn TCNTn CTC TOP TOP 1 TOP BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 ...

Page 83: ...eration to be used Modes of oper ation supported by the Timer Counter unit are Normal mode Clear Timer on Compare Match CTC mode and two types of Pulse Width Modulation PWM modes See Table 39 and Modes of Operation on page 76 Note 1 The CTC0 and PWM0 bit definition names are now obsolete Use the WGM01 0 def initions However the functionality and location of these bits are compatible with previous ...

Page 84: ...In this case the Compare Match is ignored but the set or clear is done at TOP See Phase Correct PWM Mode on page 79 for more details Table 40 Compare Output Mode non PWM Mode COM01 COM00 Description 0 0 Normal port operation OC0 disconnected 0 1 Toggle OC0 on Compare Match 1 0 Clear OC0 on Compare Match 1 1 Set OC0 on Compare Match Table 41 Compare Output Mode Fast PWM Mode 1 COM01 COM00 Descripti...

Page 85: ...OC0 pin Timer Counter Interrupt Mask Register TIMSK Bit 1 OCIE0 Timer Counter0 Output Compare Match Interrupt Enable When the OCIE0 bit is written to one and the I bit in the Status Register is set one the Timer Counter0 Compare Match interrupt is enabled The corresponding interrupt is executed if a Compare Match in Timer Counter0 occurs i e when the OCF0 bit is set in the Timer Counter Interrupt ...

Page 86: ...g vector Alternatively OCF0 is cleared by writing a logic one to the flag When the I bit in SREG OCIE0 Timer Counter0 Com pare Match Interrupt Enable and OCF0 are set one the Timer Counter0 Compare Match Interrupt is executed Bit 0 TOV0 Timer Counter0 Overflow Flag The bit TOV0 is set one when an overflow occurs in Timer Counter0 TOV0 is cleared by hardware when executing the corresponding interru...

Page 87: ...equals the prescaler divisor 8 64 256 or 1024 It is possible to use the Prescaler Reset for synchronizing the Timer Counter to program execution However care must be taken if the other Timer Counter that shares the same prescaler also uses prescaling A prescaler reset will affect the prescaler period for all Timer Counters it is connected to External Clock Source An external clock source applied t...

Page 88: ...I O 2 5 An external clock source can not be prescaled Figure 39 Prescaler for Timer Counter0 and Timer Counter1 1 Note 1 The synchronization logic on the input pins T1 T0 is shown in Figure 38 Special Function IO Register SFIOR Bit 0 PSR10 Prescaler Reset Timer Counter1 and Timer Counter0 When this bit is written to one the Timer Counter1 and Timer Counter0 prescaler will be reset The bit will be ...

Page 89: ...ndent Interrupt Sources TOV1 OCF1A OCF1B and ICF1 Overview Most register and bit references in this section are written in general form A lower case n replaces the Timer Counter number and a lower case x replaces the Output Com pare unit channel However when using the register or bit defines in a program the precise form must be used i e TCNT1 for accessing Timer Counter1 counter value and so on A...

Page 90: ... Register TIMSK TIFR and TIMSK are not shown in the figure since these registers are shared by other timer units The Timer Counter can be clocked internally via the prescaler or by an external clock source on the T1 pin The Clock Select logic block controls which clock source and edge the Timer Counter uses to increment or decrement its value The Timer Counter is inactive when no clock source is s...

Page 91: ...ons The following definitions are used extensively throughout the document Compatibility The 16 bit Timer Counter has been updated and improved from previous versions of the 16 bit AVR Timer Counter This 16 bit Timer Counter is fully compatible with the earlier version regarding All 16 bit Timer Counter related I O Register address locations including Timer Interrupt Registers Bit locations inside...

Page 92: ...he high byte must be written before the low byte For a 16 bit read the low byte must be read before the high byte The following code examples show how to access the 16 bit Timer Registers assuming that no interrupts update the temporary register The same principle can be used directly for accessing the OCR1A B and ICR1 Registers Note that when using C the compiler handles the 16 bit access Note 1 ...

Page 93: ...returns the TCNT1 value in the r17 r16 register pair Assembly Code Example 1 TIM16_ReadTCNT1 Save Global Interrupt Flag in r18 SREG Disable interrupts cli Read TCNT1 into r17 r16 in r16 TCNT1L in r17 TCNT1H Restore Global Interrupt Flag out SREG r18 ret C Code Example 1 unsigned int TIM16_ReadTCNT1 void unsigned char sreg unsigned int i Save Global Interrupt Flag sreg SREG Disable interrupts _CLI ...

Page 94: ...one 16 bit register where the high byte is the same for all registers written then the high byte only needs to be written once However note that the same rule of atomic operation described previously also applies in this case Assembly Code Example 1 TIM16_WriteTCNT1 Save Global Interrupt Flag in r18 SREG Disable interrupts cli Set TCNT1 to r17 r16 out TCNT1H r17 out TCNT1L r16 Restore Global Inter...

Page 95: ... the TCNT1H I O location the CPU accesses the high byte temporary register TEMP The temporary register is updated with the TCNT1H value when the TCNT1L is read and TCNT1H is updated with the temporary register value when TCNT1L is written This allows the CPU to read or write the entire 16 bit counter value within one clock cycle via the 8 bit data bus It is impor tant to notice that there are spec...

Page 96: ... not directly a part of the Input Capture unit are gray shaded The small n in register and bit names indicates the Timer Counter number Figure 42 Input Capture Unit Block Diagram When a change of the logic level an event occurs on the Input Capture pin ICP1 alternatively on the Analog Comparator output ACO and this change confirms to the setting of the edge detector a capture will be triggered Whe...

Page 97: ... can be triggered by software by controlling the port of the ICP1 pin Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme The noise canceler input is monitored over four samples and all four must be equal for changing the output that in turn is used by the edge detector The noise canceler is enabled by setting the Input Capture Noise Canceler ICNC1 ...

Page 98: ... on page 101 A special feature of output compare unit A allows it to define the Timer Counter TOP value i e counter resolution In addition to the counter resolution the TOP value defines the period time for waveforms generated by the Waveform Generator Figure 43 shows a block diagram of the output compare unit The small n in the regis ter and bit names indicates the device number n 1 for Timer Cou...

Page 99: ...re FOC1x bit Forcing Compare Match will not set the OCF1x Flag or reload clear the timer but the OC1x pin will be updated as if a real Compare Match had occurred the COM11 0 bits settings define whether the OC1x pin is set cleared or toggled Compare Match Blocking by TCNT1 Write All CPU writes to the TCNT1 Register will block any Compare Match that occurs in the next timer clock cycle even when th...

Page 100: ...er DDR for the port pin The Data Direction Register bit for the OC1x pin DDR_OC1x must be set as output before the OC1x value is visible on the pin The port override function is generally independent of the Waveform Generation mode but there are some exceptions Refer to Table 45 Table 46 and Table 47 for details The design of the output compare pin logic allows initialization of the OC1x state bef...

Page 101: ...1 Flag in this case behaves like a 17th bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV1 Flag the timer resolution can be increased by software There are no special cases to consider in the Normal mode a new counter value can be written anytime The Input Capture unit is easy to use in Normal mode However observe that t...

Page 102: ...le on the port pin unless the data direction for the pin is set to output DDR_OC1A 1 The waveform generated will have a maximum frequency of fOC1A fclk_I O 2 when OCR1A is set to zero 0x0000 The waveform frequency is defined by the following equation The N variable represents the prescaler factor 1 8 64 256 or 1024 As for the Normal mode of operation the TOV1 Flag is set in the same timer clock cy...

Page 103: ...s Figure 46 Fast PWM Mode Timing Diagram The Timer Counter Overflow Flag TOV1 is set each time the counter reaches TOP In addition the OC1A or ICF1 Flag is set at the same timer clock cycle as TOV1 is set when either OCR1A or ICR1 is used for defining the TOP value If one of the interrupts are enabled the interrupt handler routine can be used for updating the TOP and com pare values When changing ...

Page 104: ...or 1024 The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the fast PWM mode If the OCR1x is set equal to BOTTOM 0x0000 the output will be a narrow spike for each TOP 1 timer clock cycle Setting the OCR1x equal to TOP will result in a constant high or low output depending on the polar ity of the output set by the COM1x1 0 bits A frequency wi...

Page 105: ...set each time the counter reaches BOT TOM When either OCR1A or ICR1 is used for defining the TOP value the OC1A or ICF1 Flag is set accordingly at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value at TOP The interrupt flags can be used to gener ate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP value the program mus...

Page 106: ...M the output will be continuously low and if set equal to TOP the output will be continuously high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP value WGM13 0 11 and COM1A1 0 1 the OC1A output will toggle with a 50 duty cycle Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation or ...

Page 107: ... is used for defining the TOP value the OC1A or ICF1 Flag set when TCNT1 has reached TOP The interrupt flags can then be used to generate an interrupt each time the counter reaches the TOP or BOTTOM value When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the compare registers If the TOP value is lower than any of the compare regist...

Page 108: ...s for the OCR1x Register represents special cases when generating a PWM waveform output in the phase correct PWM mode If the OCR1x is set equal to BOTTOM the output will be continuously low and if set equal to TOP the output will be set to high for non inverted PWM mode For inverted PWM the output will have the opposite logic values If OCR1A is used to define the TOP value WGM13 0 9 and COM1A1 0 1...

Page 109: ...d be replaced by BOTTOM TOP 1 by BOTTOM 1 and so on The same renaming applies for modes that set the TOV1 Flag at BOTTOM Figure 51 Timer Counter Timing Diagram no Prescaling Figure 52 shows the same timing data but with the prescaler enabled OCFnx OCRnx TCNTn OCRnx Value OCRnx 1 OCRnx OCRnx 1 OCRnx 2 clkI O clkTn clkI O 8 TOVn FPWM and ICFn if used as TOP OCRnx Update at TOP TCNTn CTC and FPWM TCN...

Page 110: ...g to the OC1A or OC1B pin must be set in order to enable the output driver When the OC1A or OC1B is connected to the pin the function of the COM1x1 0 bits is dependent of the WGM13 0 bits setting Table 45 shows the COM1x1 0 bit functionality when the WGM13 0 bits are set to a normal or a CTC mode non PWM TOVn FPWM and ICFn if used as TOP OCRnx Update at TOP TCNTn CTC and FPWM TCNTn PC and PFC PWM ...

Page 111: ...OC1A FOC1B bits are implemented as strobes Therefore it is the value present in the COM1x1 0 bits that determine the effect of the forced compare A FOC1A FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer on Compare Match CTC mode using OCR1A as TOP The FOC1A FOC1B bits are always read as zero Bit 1 0 WGM11 0 Waveform Generation Mode Table 46 Compare Output Mod...

Page 112: ...Waveform Generation Mode Bit Description 1 Mode WGM13 WGM12 CTC1 WGM11 PWM11 WGM10 PWM10 Timer Counter Mode of Operation TOP Update of OCR1x at TOV1 Flag Set on 0 0 0 0 0 Normal 0xFFFF Immediate MAX 1 0 0 0 1 PWM Phase Correct 8 bit 0x00FF TOP BOTTOM 2 0 0 1 0 PWM Phase Correct 9 bit 0x01FF TOP BOTTOM 3 0 0 1 1 PWM Phase Correct 10 bit 0x03FF TOP BOTTOM 4 0 1 0 0 CTC OCR1A Immediate MAX 5 0 1 0 1 ...

Page 113: ...as TOP value see description of the WGM13 0 bits located in the TCCR1A and the TCCR1B Register the ICP1 is disconnected and consequently the Input Capture function is disabled Bit 5 Reserved Bit This bit is reserved for future use For ensuring compatibility with future devices this bit must be written to zero when TCCR1B is written Bit 4 3 WGM13 2 Waveform Generation Mode See TCCR1A Register descr...

Page 114: ... high and low bytes are written simultaneously when the CPU writes to these registers the access is performed using an 8 bit temporary high byte register TEMP This temporary register is shared by all the other 16 bit registers See Accessing 16 bit Registers on page 92 Input Capture Register 1 ICR1H and ICR1L The Input Capture is updated with the counter TCNT1 value each time an event occurs on the...

Page 115: ...r Counter1 output compare A match interrupt is enabled The corresponding Interrupt Vector see Interrupts on page 46 is executed when the OCF1A Flag located in TIFR is set Bit 3 OCIE1B Timer Counter1 Output Compare B Match Interrupt Enable When this bit is written to one and the I flag in the Status Register is set interrupts glo bally enabled the Timer Counter1 output compare B match interrupt is ...

Page 116: ...y cleared when the Output Compare Match A Interrupt Vector is executed Alternatively OCF1A can be cleared by writing a logic one to its bit location Bit 3 OCF1B Timer Counter1 Output Compare B Match Flag This flag is set in the timer clock cycle after the counter TCNT1 value matches the Out put Compare Register B OCR1B Note that a Forced Output Compare FOC1B strobe will not set the OCF1B Flag OCF1...

Page 117: ... A simplified block diagram of the 8 bit Timer Counter is shown in Figure 53 For the actual placement of I O pins refer to Pinout ATmega8535 on page 2 CPU accessible I O Registers including I O bits and I O pins are shown in bold The device specific I O Register and bit locations are listed in the 8 bit Timer Counter Register Description on page 128 Figure 53 8 bit Timer Counter Block Diagram Time...

Page 118: ...ill also set the Compare Flag OCF2 which can be used to generate an output compare interrupt request Definitions Many register and bit references in this section are written in general form A lower case n replaces the Timer Counter number in this case 2 However when using the register or bit defines in a program the precise form must be used i e TCNT2 for accessing Timer Counter2 counter value and...

Page 119: ...en how the counter behaves counts and how waveforms are generated on the output compare output OC2 For more details about advanced counting sequences and waveform generation see Modes of Operation on page 122 The Timer Counter Overflow Flag TOV2 is set according to the mode of operation selected by the WGM21 0 bits TOV2 can be used for generating a CPU interrupt Output Compare Unit The 8 bit compa...

Page 120: ...ne whether the OC2 pin is set cleared or toggled Compare Match Blocking by TCNT2 Write All CPU write operations to the TCNT2 Register will block any Compare Match that occurs in the next timer clock cycle even when the timer is stopped This feature allows OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when the Timer Counter clock is enabled Using the Output Compa...

Page 121: ...if either of the COM21 0 bits are set However the OC2 pin direc tion input or output is still controlled by the Data Direction Register DDR for the port pin The Data Direction Register bit for the OC2 pin DDR_OC2 must be set as output before the OC2 value is visible on the pin The port override function is independent of the Waveform Generation mode The design of the output compare pin logic allow...

Page 122: ...m 0x00 In normal operation the Timer Counter Overflow Flag TOV2 will be set in the same timer clock cycle as the TCNT2 becomes zero The TOV2 Flag in this case behaves like a ninth bit except that it is only set not cleared However combined with the timer overflow interrupt that automatically clears the TOV2 Flag the timer resolution can be increased by software There are no special cases to consid...

Page 123: ...the same timer clock cycle that the counter counts from MAX to 0x00 Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode WGM21 0 3 provides a high fre quency PWM waveform generation option The fast PWM differs from the other PWM option by its single slope operation The counter counts from BOTTOM to MAX then restarts from BOTTOM In non inverting Compare Output mode the Output Compare OC2 ...

Page 124: ...PWM frequency for the output can be calculated by the following equation The N variable represents the prescale factor 1 8 32 64 128 256 or 1024 The extreme values for the OCR2 Register represent special cases when generating a PWM waveform output in the fast PWM mode If the OCR2 is set equal to BOTTOM the output will be a narrow spike for each MAX 1 timer clock cycle Setting the OCR2 equal to MAX...

Page 125: ...The timing diagram for the phase correct PWM mode is shown on Figure 59 The TCNT2 value is in the timing diagram shown as a histogram for illustrating the dual slope operation The diagram includes non inverted and inverted PWM outputs The small horizontal line marks on the TCNT2 slopes repre sent compare matches between OCR2 and TCNT2 Figure 59 Phase Correct PWM Mode Timing Diagram The Timer Count...

Page 126: ...ike in Figure 59 When the OCR2 value is MAX the OCn pin value is the same as the result of a down counting Compare Match To ensure symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up counting Compare Match The timer starts counting from a value higher than the one in OCR2 and for that reason misses the Compare Match and hence the OCn change that would have happened o...

Page 127: ... of OCF2 in all modes except CTC mode Figure 62 Timer Counter Timing Diagram Setting of OCF2 with Prescaler fclk_I O 8 Figure 63 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode TOVn TCNTn MAX 1 MAX BOTTOM BOTTOM 1 clkI O clkTn clkI O 8 OCFn OCRn TCNTn OCRn Value OCRn 1 OCRn OCRn 1 OCRn 2 clkI O clkTn clkI O 8 ...

Page 128: ...a strobe Therefore it is the value present in the COM21 0 bits that determines the effect of the forced compare A FOC2 strobe will not generate any interrupt nor will it clear the timer in CTC mode using OCR2 as TOP The FOC2 bit is always read as zero Bit 6 3 WGM21 0 Waveform Generation Mode These bits control the counting sequence of the counter the source for the maximum TOP counter value and wh...

Page 129: ...e 53 shows the COM21 0 bit functionality when the WGM21 0 bits are set to fast PWM mode Note 1 A special case occurs when OCR2 equals TOP and COM21 is set In this case the Compare Match is ignored but the set or clear is done at TOP See Fast PWM Mode on page 123 for more details Table 51 Waveform Generation Mode Bit Description 1 Mode WGM21 CTC2 WGM20 PWM2 Timer Counter Mode of Operation TOP Updat...

Page 130: ...r clock Modifying the counter TCNT2 while the counter is running introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register Table 54 Compare Output Mode Phase Correct PWM Mode 1 COM21 COM20 Description 0 0 Normal port operation OC2 disconnected 0 1 Reserved 1 0 Clear OC2 on Compare Match when up counting Set OC2 on Compare Match when down counting 1 1 Set OC2 on Compare Match...

Page 131: ... Compare Register 2 Update Busy When Timer Counter2 operates asynchronously and OCR2 is written this bit becomes set When OCR2 has been updated from the temporary storage register this bit is cleared by hardware A logical zero in this bit indicates that OCR2 is ready to be updated with a new value Bit 0 TCR2UB Timer Counter Control Register 2 Update Busy When Timer Counter2 operates asynchronously...

Page 132: ...l the written register has been updated if Timer Counter2 is used to wake up the device Otherwise the MCU will enter sleep mode before the changes are effective This is particularly important if the Output Compare 2 interrupt is used to wake up the device since the output compare function is disabled during writing to OCR2 or TCNT2 If the write cycle is not finished and the MCU enters sleep mode b...

Page 133: ...dure for reading TCNT2 is thus as follows 1 Write any value to either of the registers OCR2 or TCCR2 2 Wait for the corresponding Update Busy Flag to be cleared 3 Read TCNT2 During asynchronous operation the synchronization of the interrupt flags for the asynchronous timer takes three processor cycles plus one timer cycle The timer is therefore advanced by at least one before the processor can rea...

Page 134: ...caler Figure 64 Prescaler for Timer Counter2 The clock source for Timer Counter2 is named clkT2S clkT2S is by default connected to the main system I O clock clkIO By setting the AS2 bit in ASSR Timer Counter2 is asyn chronously clocked from the TOSC1 pin This enables use of Timer Counter2 as a Real Time Counter RTC When AS2 is set pins TOSC1 and TOSC2 are disconnected from Port C A crystal can the...

Page 135: ...operation is performed Writing a zero to this bit will have no effect This bit will always be read as zero if Timer Counter2 is clocked by the internal CPU clock If this bit is written when Timer Counter2 is operating in asynchronous mode the bit will remain one until the prescaler has been reset Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 ACME PUD PSR2 PSR10 SFIOR Read Write R W R W R W R R W R W R W R...

Page 136: ...on between Master and Slave CPUs with SPI is shown in Figure 66 The system consists of two Shift Registers and a Master clock generator The SPI Mas ter initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave Master and Slave prepare the data to be sent in their respective Shift Registers and the Master generates the required clock pulses on the SCK line to i...

Page 137: ...uested The Slave may continue to place new data to be sent into SPDR before reading the incoming data The last incoming byte will be kept in the buffer register for later use Figure 66 SPI Master Slave Interconnection The system is single buffered in the transmit direction and double buffered in the receive direction This means that bytes to be transmitted cannot be written to the SPI Data Registe...

Page 138: ...sion DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins DD_MOSI DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins For example if MOSI is placed on pin PB5 replace DD_MOSI with DDB5 and DDR_SPI with DDRB Table 56 SPI Pin Overrides 1 Pin Direction Master SPI Direction Slave SPI MOSI User Defined Input MISO Input ...

Page 139: ...SPCR r17 ret SPI_MasterTransmit Start transmission of data r16 out SPDR r16 Wait_Transmit Wait for transmission complete sbis SPSR SPIF rjmp Wait_Transmit ret C Code Example 1 void SPI_MasterInit void Set MOSI and SCK output all others input DDR_SPI 1 DD_MOSI 1 DD_SCK Enable SPI Master set clock rate fck 16 SPCR 1 SPE 1 MSTR 1 SPR0 void SPI_MasterTransmit char cData Start transmission SPDR cData W...

Page 140: ...ll others input ldi r17 1 DD_MISO out DDR_SPI r17 Enable SPI ldi r17 1 SPE out SPCR r17 ret SPI_SlaveReceive Wait for reception complete sbis SPSR SPIF rjmp SPI_SlaveReceive Read received data and return in r16 SPDR ret C Code Example 1 void SPI_SlaveInit void Set MISO output all others input DDR_SPI 1 DD_MISO Enable SPI SPCR 1 SPE char SPI_SlaveReceive void Wait for reception complete while SPSR ...

Page 141: ...ing to send data to it To avoid bus contention the SPI system takes the following actions 1 The MSTR bit in SPCR is cleared and the SPI system becomes a Slave As a result of the SPI becoming a Slave the MOSI and SCK pins become inputs 2 The SPIF Flag in SPSR is set and if the SPI interrupt is enabled and the I bit in SREG is set the interrupt routine will be executed Thus when interrupt driven SPI...

Page 142: ...7 and Figure 68 for an example The CPOL functionality is summarized below Bits 1 0 SPR1 SPR0 SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master SPR1 and SPR0 have no effect on the Slave The relationship between SCK and the Oscillator Clock frequency fosc is shown in the following table Table 57 CPOL Functionality CPOL Leading Edge Trailing Edge 0...

Page 143: ...se bits are reserved bits in the ATmega8535 and will always read as zero Bit 0 SPI2X Double SPI Speed Bit When this bit is written logic one the SPI speed SCK Frequency will be doubled when the SPI is in Master mode see Table 59 This means that the minimum SCK period will be two CPU clock periods When the SPI is configured as Slave the SPI is only guaran teed to work at fosc 4 or lower The SPI int...

Page 144: ...SPI Transfer Format with CPHA 1 Table 60 CPOL Functionality Leading Edge Trailing Edge SPI Mode CPOL 0 CPHA 0 Sample Rising Setup Falling 0 CPOL 0 CPHA 1 Setup Rising Sample Falling 1 CPOL 1 CPHA 0 Sample Falling Setup Rising 2 CPOL 1 CPHA 1 Setup Falling Sample Rising 3 Bit 1 Bit 6 LSB MSB SCK CPOL 0 mode 0 SAMPLE I MOSI MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SCK CPOL 1 mode 2 SS MSB LSB Bit 6 ...

Page 145: ...se Start Bit Detection and Digital Low Pass Filter Three Separate Interrupts on TX Complete TX Data Register Empty and RX Complete Multi processor Communication Mode Double Speed Asynchronous Communication Mode Overview A simplified block diagram of the USART Transmitter is shown in Figure 69 CPU acces sible I O Registers and I O pins are shown in bold Figure 69 USART Block Diagram 1 Note 1 Refer ...

Page 146: ...cases A second buffer register has been added The two buffer registers operate as a circular FIFO buffer Therefore the UDR must only be read once for each incoming data More important is the fact that the Error Flags FE and DOR and the ninth data bit RXB8 are buffered with the data in the receive buffer Therefore the status bits must always be read before the UDR Register is read Otherwise the err...

Page 147: ...unning at sys tem clock fosc is loaded with the UBRR value each time the counter has counted down to zero or when the UBRRL Register is written A clock is generated each time the counter reaches zero This clock is the baud rate generator clock output fosc UBRR 1 The Transmitter divides the baud rate generator clock output by 2 8 or 16 depending on mode The baud rate generator output is used direct...

Page 148: ...ed For the Transmitter there are no downsides External Clock External clocking is used by the synchronous slave modes of operation The description in this section refers to Figure 70 for details External clock input from the XCK pin is sampled by a synchronization register to mini mize the chance of meta stability The output from the synchronization register must then pass through an edge detector...

Page 149: ...d to be one character of data bits with synchronization bits start and stop bits and optionally a parity bit for error checking The USART accepts all 30 combinations of the following as valid frame formats 1 start bit 5 6 7 8 or 9 data bits no even or odd parity bit 1 or 2 stop bits A frame starts with the start bit followed by the least significant data bit Then the next data bits up to a total o...

Page 150: ...he relation between the parity bit and data bits is as follows Peven Parity bit using even parity Podd Parity bit using odd parity dn Data bit n of the character If used the parity bit is located between the last data bit and first stop bit of a serial frame USART Initialization The USART has to be initialized before any communication can take place The initial ization process normally consists of...

Page 151: ...at as parame ters disable interrupts and so on However many applications use a fixed setting of the baud and control registers and for these types of applications the initialization code can be placed directly in the main routine or be combined with initialization code for other I O modules Assembly Code Example 1 USART_Init Set baud rate out UBRRH r17 out UBRRL r16 Enable Receiver and Transmitter...

Page 152: ...last stop bit of the previ ous frame is transmitted When the Shift Register is loaded with new data it will transfer one complete frame at the rate given by the baud register U2X bit or by XCK depending on mode of operation The following code examples show a simple USART transmit function based on polling of the Data Register Empty UDRE Flag When using frames with less than eight bits the most sig...

Page 153: ...th flags can be used for generating interrupts The Data Register Empty UDRE Flag indicates whether the transmit buffer is ready to receive new data This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted that has not yet been moved into the Shift Register For compatibility with future devices always write this bit to zero when writing ...

Page 154: ...bus immediately after completing the transmission When the Transmit Compete Interrupt Enable TXCIE bit in UCSRB is set the USART Transmit Complete Interrupt will be executed when the TXC Flag becomes set pro vided that global interrupts are enabled When the transmit complete interrupt is used the interrupt handling routine does not have to clear the TXC Flag this is done automat ically when the in...

Page 155: ...ver When the first stop bit is received i e a complete serial frame is present in the receive Shift Register the contents of the Shift Register will be moved into the receive buffer The receive buffer can then be read by reading the UDR I O location The following code example shows a simple USART receive function based on polling of the Receive Complete RXC Flag When using frames with less than ei...

Page 156: ...at handles both 9 bit characters and the status bits Assembly Code Example 1 USART_Receive Wait for data to be received sbis UCSRA RXC rjmp USART_Receive Get status and 9th bit then data from buffer in r18 UCSRA in r17 UCSRB in r16 UDR If error return 1 andi r18 1 FE 1 DOR 1 PE breq USART_ReceiveNoError ldi r17 HIGH 1 ldi r16 LOW 1 USART_ReceiveNoError Filter the 9th bit then return lsr r17 andi r...

Page 157: ...e UCSRA is written for upward compatibility of future USART implementations None of the error flags can generate interrupts The Frame Error FE Flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer The FE Flag is zero when the stop bit was correctly read as one and the FE Flag will be one when the stop bit was incorrect zero This flag can be used for...

Page 158: ...sh the receive buffer Note 1 See About Code Examples on page 7 Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchro nous data reception The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames at the RxD pin The data recovery logic samples and low pass filters eac...

Page 159: ... Double Speed mode Figure 74 shows the sam pling of the data bits and the parity bit Each of the samples is given a number that is equal to the state of the recovery unit Figure 74 Sampling of Data and Parity Bit The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit The center samples are em...

Page 160: ...nerated baud rate of the Receiver does not have a similar see Table 62 base frequency the Receiver will not be able to synchronize the frames to the start bit The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate D Sum of character size and parity size D 5 to 10 bit S Samples per bit S 16 for Normal Speed mode and S 8 for Double Speed ...

Page 161: ... can not always do an exact division of the system frequency to get the baud rate wanted In this case an UBRR value that gives an acceptable low error can be used if possible Table 62 Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode U2X 0 D Data Parity Bit Rslow Rfast Max Total Error Recommended Max Receiver Error 5 93 20 106 67 6 67 6 8 3 0 6 94 12 105 79 5 79 5 88 2 5 7 94 81 1...

Page 162: ...it character frame format UCSZ 7 The ninth bit TXB8 must be set when an address frame TXB8 1 or cleared when a data frame TXB 0 is being transmitted The Slave MCUs must in this case be set to use a 9 bit character frame format The following procedure should be used to exchange data in Multi processor Communi cation Mode 1 All Slave MCUs are in Multi processor Communication Mode MPCM in UCSRA is se...

Page 163: ...peration the UBRRH value will be updated If URSEL is one the UCSRC setting will be updated The following code examples show how to access the two registers Note 1 See About Code Examples on page 7 As the code examples illustrate write accesses of the two registers are relatively unaf fected of the sharing of I O location Assembly Code Examples 1 Set UBRRH to 2 ldi r16 0x02 out UBRRH r16 Set the US...

Page 164: ...ssembly code example returns the UCSRC value in r16 Reading the UBRRH contents is not an atomic operation and therefore it can be read as an ordinary register as long as the previous instruction did not access the register location USART Register Description USART I O Data Register UDR The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I O address referr...

Page 165: ...n the transmit buffer UDR The TXC Flag bit is automatically cleared when a Transmit Complete interrupt is executed or it can be cleared by writing a one to its bit location The TXC Flag can generate a Transmit Complete interrupt see description of the TXCIE bit Bit 5 UDRE USART Data Register Empty The UDRE Flag indicates if the transmit buffer UDR is ready to receive new data If UDRE is one the bu...

Page 166: ... UDRIE USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDRE Flag A Data Register Empty inter rupt will be generated only if the UDRIE bit is written to one the Global Interrupt Flag in SREG is written to one and the UDRE bit in UCSRA is set Bit 4 RXEN Receiver Enable Writing this bit to one enables the USART Receiver The Receiver will override normal por...

Page 167: ...e 163 section which describes how to access this register Bit 7 URSEL Register Select This bit selects between accessing the UCSRC or the UBRRH Register It is read as one when reading UCSRC The URSEL must be one when writing the UCSRC Bit 6 UMSEL USART Mode Select This bit selects between asynchronous and synchronous mode of operation Bit 7 6 5 4 3 2 1 0 URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPO...

Page 168: ...lects the number of stop bits to be inserted by the Transmitter The Receiver ignores this setting Bit 2 1 UCSZ1 0 Character Size The UCSZ1 0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits character size in a frame the Receiver and Transmitter use Bit 0 UCPOL Clock Polarity Table 65 UPM Bits Settings UPM1 UPM0 Parity Mode 0 0 Disabled 0 1 Reserved 1 0 Enabled Even Parity 1 1...

Page 169: ...d for future use For compatibility with future devices these bit must be written to zero when UBRRH is written Bit 11 0 UBRR11 0 USART Baud Rate Register This is a 12 bit register which contains the USART Baud Rate The UBRRH contains the four most significant bits and the UBRRL contains the eight least significant bits of the USART baud rate Ongoing transmissions by the Transmitter and Receiver wi...

Page 170: ...udRateClosest Match BaudRate 1 100 Table 69 Examples of UBRR Settings for Commonly Used Oscillator Frequencies Baud Rate bps fosc 1 0000 MHz fosc 1 8432 MHz fosc 2 0000 MHz U2X 0 U2X 1 U2X 0 U2X 1 U2X 0 U2X 1 UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error UBRR Error 2400 25 0 2 51 0 2 47 0 0 95 0 0 51 0 2 103 0 2 4800 12 0 2 25 0 2 23 0 0 47 0 0 25 0 2 51 0 2 9600 6 7 0 12 0 2 11 0 0 23 0 ...

Page 171: ...91 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4k 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2k 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8k 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4k 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6k 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8k 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2k 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4k 0 0 0 1 0 0 0 8 5 1 8 ...

Page 172: ... 0 2 103 0 2 71 0 0 143 0 0 95 0 0 191 0 0 14 4k 34 0 8 68 0 6 47 0 0 95 0 0 63 0 0 127 0 0 19 2k 25 0 2 51 0 2 35 0 0 71 0 0 47 0 0 95 0 0 28 8k 16 2 1 34 0 8 23 0 0 47 0 0 31 0 0 63 0 0 38 4k 12 0 2 25 0 2 17 0 0 35 0 0 23 0 0 47 0 0 57 6k 8 3 5 16 2 1 11 0 0 23 0 0 15 0 0 31 0 0 76 8k 6 7 0 12 0 2 8 0 0 17 0 0 11 0 0 23 0 0 115 2k 3 8 5 8 3 5 5 0 0 11 0 0 7 0 0 15 0 0 230 4k 1 8 5 3 8 5 2 0 0 5...

Page 173: ... 103 0 2 207 0 2 119 0 0 239 0 0 129 0 2 259 0 2 14 4k 68 0 6 138 0 1 79 0 0 159 0 0 86 0 2 173 0 2 19 2k 51 0 2 103 0 2 59 0 0 119 0 0 64 0 2 129 0 2 28 8k 34 0 8 68 0 6 39 0 0 79 0 0 42 0 9 86 0 2 38 4k 25 0 2 51 0 2 29 0 0 59 0 0 32 1 4 64 0 2 57 6k 16 2 1 34 0 8 19 0 0 39 0 0 21 1 4 42 0 9 76 8k 12 0 2 25 0 2 14 0 0 29 0 0 15 1 7 32 1 4 115 2k 8 3 5 16 2 1 9 0 0 19 0 0 10 1 4 21 1 4 230 4k 3 8...

Page 174: ...ontroller applica tions The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi directional bus lines one for clock SCL and one for data SDA The only external hardware needed to implement the bus is a single pull up resistor for each of the TWI bus lines All devices connected to the bus have individual addresses and mechanisms for resolving bus co...

Page 175: ...nd Frame Format Transferring Bits Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line The level of the data line must be stable when the clock line is high The only exception to this rule is for generating start and stop conditions Figure 77 Data Validity START and STOP Conditions The Master initiates and terminates a data transmission The transmission is initiated...

Page 176: ...transmit the same mes sage to several slaves in the system When the general call address followed by a Write bit is transmitted on the bus all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle The following data packets will then be received by all the slaves that acknowledged the general call Note that transmitting the general call address followed by a Rea...

Page 177: ...taken in order to ensure that transmissions will proceed as normal even if two or more masters initiate a transmission at the same time Two problems arise in multi mas ter systems An algorithm must be implemented allowing only one of the Masters to complete the transmission All other masters should cease transmission when they discover that they have lost the selection process This selection proce...

Page 178: ...ote that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value The losing master should immediately go to Slave mode checking if it is being addressed by the winning master The SDA line should be left high but losing masters are allowed to generate a clock signal until the end of the current data or address packet Arbitration will continue unt...

Page 179: ...e 84 Overview of the TWI Module SCL and SDA Pins These pins interface the AVR TWI with the rest of the MCU system The output drivers contain a slew rate limiter in order to conform to the TWI specification The input stages contain a spike suppression unit removing spikes shorter than 50 ns Note that the inter nal pull ups in the AVR pads can be enabled by setting the PORT bits corresponding to the...

Page 180: ...P conditions even when the AVR MCU is in one of the sleep modes enabling the MCU to wake up if addressed by a Master If the TWI has initiated a transmission as Master the Arbitration Detection hardware continuously monitors the transmission trying to determine if arbitration is in process If the TWI has lost an arbitration the Control Unit is informed Correct action can then be taken and appropria...

Page 181: ...R while the register is inaccessible Bit 7 TWINT TWI Interrupt Flag This bit is set by hardware when the TWI has finished its current job and expects appli cation software response If the I bit in SREG and TWIE in TWCR are set the MCU will jump to the TWI Interrupt Vector While the TWINT Flag is set the SCL low period is stretched The TWINT Flag must be cleared by software by writing a logic one t...

Page 182: ...t is cleared automatically In Slave mode setting the TWSTO bit can be used to recover from an error condition This will not generate a STOP condition but the TWI returns to a well defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state Bit 3 TWWC TWI Write Collision Flag The TWWC bit is set when attempting to write to the TWI Data Register TWDR when TWINT is low...

Page 183: ...ccurs when the TWI Interrupt Flag TWINT is set by hardware Note that the Data Register cannot be initialized by the user before the first interrupt occurs The data in TWDR remains stable as long as TWINT is set While data is shifted out data on the bus is simultaneously shifted in TWDR always contains the last byte present on the bus except after a wake up from a sleep mode by the TWI interrupt In...

Page 184: ...d to enable recognition of the general call address 0x00 There is an associated address comparator that looks for the slave address or general call address if enabled in the received serial address If a match is found an interrupt request is generated Bits 7 1 TWA TWI Slave Address Register These seven bits constitute the slave address of the TWI unit Bit 0 TWGCE TWI General Call Recognition Enabl...

Page 185: ...e TWI hardware to transmit a START condition Which value to write is described later on However it is important that the TWINT bit is set in the value written Writing a one to TWINT clears the flag The TWI will not start any operation as long as the TWINT bit in TWCR is set Immediately after the application has cleared TWINT the TWI will initiate transmission of the START condition 2 When the STAR...

Page 186: ...ission of the data packet 6 When the data packet has been transmitted the TWINT Flag in TWCR is set and TWSR is updated with a status code indicating that the data packet has suc cessfully been sent The status code will also reflect whether a Slave acknowledged the packet or not 7 The application software should now examine the value of TWSR to make sure that the data packet was successfully trans...

Page 187: ...start transmission of address 4 wait2 in r16 TWCR sbrs r16 TWINT rjmp wait2 while TWCR 1 TWINT Wait for TWINT Flag set This indicates that the SLA W has been transmitted and ACK NACK has been received 5 in r16 TWSR andi r16 0xF8 cpi r16 MT_SLA_ACK brne ERROR if TWSR 0xF8 MT_SLA_ACK ERROR Check value of TWI Status Register Mask prescaler bits If status different from MT_SLA_ACK go to ERROR ldi r16 ...

Page 188: ...ures contain the following abbreviations S START condition Rs REPEATED START condition R Read bit high level at SDA W Write bit low level at SDA A Acknowledge bit low level at SDA A Not acknowledge bit high level at SDA Data 8 bit data byte P STOP condition SLA Slave Address In Figure 87 to Figure 93 circles are used to indicate that the TWINT Flag is set The numbers in the circles show the status...

Page 189: ...08 see Table 75 In order to enter MT mode SLA W must be transmitted This is done by writ ing SLA W to TWDR Thereafter the TWINT bit should be cleared by writing it to one to continue the transfer This is accomplished by writing the following value to TWCR When SLA W have been transmitted and an acknowledgement bit has been received TWINT is set again and a number of status codes in TWSR are possib...

Page 190: ... be transmitted and ACK or NOT ACK will be received Repeated START will be transmitted STOP condition will be transmitted and TWSTO Flag will be reset STOP condition followed by a START condition will be transmitted and TWSTO Flag will be reset 0x20 SLA W has been transmitted NOT ACK has been received Load data byte or No TWDR action or No TWDR action or No TWDR action 0 1 0 1 0 0 1 1 1 1 1 1 X X ...

Page 191: ...mission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in ...

Page 192: ...08 see Table 75 In order to enter MR mode SLA R must be transmitted This is done by writing SLA R to TWDR Thereafter the TWINT bit should be cleared by writing it to one to continue the transfer This is accomplished by writing the following value to TWCR When SLA R have been transmitted and an acknowledgement bit has been received TWINT is set again and a number of status codes in TWSR are possibl...

Page 193: ...on lost in SLA R or NOT ACK bit No TWDR action or No TWDR action 0 1 0 0 1 1 X X Two wire Serial Bus will be released and not addressed Slave mode will be entered A START condition will be transmitted when the bus becomes free 0x40 SLA R has been transmitted ACK has been received No TWDR action or No TWDR action 0 0 0 0 1 1 0 1 Data byte will be received and NOT ACK will be returned Data byte will...

Page 194: ...es W A 68 Other master continues 78 B0 To corresponding states in slave mode MR MT Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration lost and addressed as slave DATA A n From master to slave From slave to master Any number of data bytes and the...

Page 195: ... 0x68 and 0x78 If the TWEA bit is reset during a transfer the TWI will return a Not Acknowledge 1 to SDA after the next received data byte This can be used to indicate that the Slave is not able to receive any more bytes While TWEA is zero the TWI does not acknowledge its own slave address However the Two wire Serial Bus is still monitored and address recognition may resume at any time by setting ...

Page 196: ... Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 Switched to the not addressed Slave mode no recognition of own SLA or GCA a START condition will be transmitted when the bus becomes free Switched to the not addressed Slave mode own SLA will be recognized GCA will be recognized if TWGCE 1 a START condition will be transmitted when the bus become...

Page 197: ... of the general call address and one or more data bytes Last data byte received is not acknowledged n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits This number contained in TWSR corresponds to a defined state of the Two wire Serial Bus The prescaler bits are zero or masked to zero P or S DATA A 80 A0 P or S A A DATA A 70 90 98 A 78 P or S ...

Page 198: ...and the write bit have been received the TWINT Flag is set and a valid status code can be read from TWSR The status code is used to determine the appropriate software action The appropriate action to be taken for each status code is detailed in Table 78 The Slave Transmitter mode may also be entered if arbitration is lost while the TWI is in the Master mode see state 0xB0 If the TWEA bit is writte...

Page 199: ...d Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should be re ceived 0xB8 Data byte in TWDR has been transmitted ACK has been received Load data byte or Load data byte X X 0 0 1 1 0 1 Last data byte will be transmitted and NOT ACK should be received Data byte will be transmitted and ACK should...

Page 200: ...are affected The SDA and SCL lines are released and no STOP condition is transmitted S SLA R A DATA A A8 B8 A B0 Reception of the own slave address and one or more data bytes Last data byte transmitted Switched to not addressed slave TWEA 0 Arbitration lost as master and addressed as slave n From master to slave From slave to master Any number of data bytes and their associated acknowledge bits Th...

Page 201: ... 3 and the Master will read the wrong data location Such a change in transfer direction is accomplished by transmitting a REPEATED START between the transmission of the address byte and reception of the data After a REPEATED START the Master keeps ownership of the bus The following figure shows the flow in this transfer Figure 94 Combining Several TWI Modes to Access a Serial EEPROM Multi master S...

Page 202: ...r outputs a zero will lose the arbitration Masters losing arbitration in SLA will switch to Slave mode to check if they are being addressed by the winning Master If addressed they will switch to SR or ST mode depending on the value of the READ WRITE bit If they are not being addressed they will switch to not addressed Slave mode or wait until the bus is free and transmit a new START condition depe...

Page 203: ...Comparator Multiplexer Enable When this bit is written logic one and the ADC is switched off ADEN in ADCSRA is zero the ADC multiplexer selects the negative input to the Analog Comparator When this bit is written logic zero AIN1 is applied to the negative input of the Analog Compar ator For a detailed description of this bit see Analog Comparator Multiplexed Input on page 205 Analog Comparator Con...

Page 204: ...r is set the Ana log Comparator Interrupt is activated When written logic zero the interrupt is disabled Bit 2 ACIC Analog Comparator Input Capture Enable When written logic one this bit enables the Input Capture function in Timer Counter1 to be triggered by the Analog Comparator The comparator output is in this case directly connected to the Input Capture front end logic making the comparator uti...

Page 205: ...lexer Enable bit ACME in SFIOR is set and the ADC is switched off ADEN in ADCSRA is zero MUX2 0 in ADMUX select the input pin to replace the negative input to the Ana log Comparator as shown in Table 81 If ACME is cleared or ADEN is set AIN1 is applied to the negative input to the Analog Comparator Table 81 Analog Comparator Multiplexed Input ACME ADEN MUX2 0 Analog Comparator Negative Input 0 x x...

Page 206: ...om the pins of Port A The single ended voltage inputs refer to 0V GND The device also supports 16 differential voltage input combinations Two of the differen tial inputs ADC1 ADC0 and ADC3 ADC2 are equipped with a programmable gain stage providing amplification steps of 0 dB 1x 20 dB 10x or 46 dB 200x on the dif ferential input voltage before the A D conversion Seven differential analog input chan...

Page 207: ...ion of ADC input pins can be selected as positive and negative inputs to the differential gain amplifier If differential channels are selected the differential gain stage amplifies the voltage dif ference between the selected input channel pair by the selected gain factor This amplified value then becomes the analog input to the ADC If single ended channels are used the gain amplifier is bypassed ...

Page 208: ...upt will trigger even if the result is lost Starting a Conversion A single conversion is started by writing a logical one to the ADC Start Conversion bit ADSC This bit stays high as long as the conversion is in progress and will be cleared by hardware when the conversion is completed If a different data channel is selected while a conversion is in progress the ADC will finish the current conversio...

Page 209: ...ns can be started by writing ADSC in ADCSRA to one ADSC can also be used to determine if a conversion is in progress The ADSC bit will be read as one during a conversion independently of how the conver sion was started Prescaling and Conversion Timing Figure 100 ADC Prescaler By default the successive approximation circuitry requires an input clock frequency between 50 kHz and 200 kHz to get maxim...

Page 210: ...and 13 5 ADC clock cycles after the start of an first conversion When a con version is complete the result is written to the ADC Data Registers and ADIF is set In Single Conversion mode ADSC is cleared simultaneously The software may then set ADSC again and a new conversion will be initiated on the first rising ADC clock edge When Auto Triggering is used the prescaler is reset when the trigger eve...

Page 211: ...version Next Conversion 3 Sample Hold MUX and REFS Update Conversion Complete MUX and REFS Update 1 2 3 4 5 6 7 8 9 10 11 12 13 MSB of Result LSB of Result ADC Clock Trigger Source ADIF ADCH ADCL Cycle Number 1 2 One Conversion Next Conversion Conversion Complete Prescaler Reset ADATE Prescaler Reset Sample Hold MUX and REFS Update 11 12 13 MSB of Result LSB of Result ADC Clock ADSC ADIF ADCH ADCL...

Page 212: ... the ADC must be switched off between conversions When Auto Triggering is used the ADC prescaler is reset before the conversion is started Since the gain stage is depen dent of a stable ADC clock prior to the conversion this conversion will not be valid By disabling and then re enabling the ADC between each conversion writing ADEN in ADCSRA to 0 then to 1 only extended conversions are performed Th...

Page 213: ... be changed one ADC clock cycle after writing one to ADSC However the simplest method is to wait for the first conversion to complete and then change the channel selection Since the next conversion has already started automati cally the next result will reflect the previous channel selection Subsequent conversions will reflect the new channel selection When switching to a differential gain channel...

Page 214: ... modes to avoid excessive power consumption If the ADC is enabled in such sleep modes and the user wants to perform differential conver sions the user is advised to switch the ADC off and on after waking up from sleep to prompt an extended conversion to get a valid result Analog Input Circuitry The Analog Input Circuitry for single ended channels is illustrated in Figure 105 An ana log source appl...

Page 215: ...nalog ground plane and keep them well away from high speed switching digital tracks 2 The AVCC pin on the device should be connected to the digital VCC supply voltage via an LC network as shown in Figure 106 3 Use the ADC noise canceler function to reduce induced noise from the CPU 4 If any ADC port pins are used as digital outputs it is essential that these do not switch while a conversion is in ...

Page 216: ...initions An n bit single ended ADC converts a voltage linearly between GND and VREF in 2n steps LSBs The lowest code is read as 0 and the highest code is read as 2n 1 Several parameters describe the deviation from the ideal behavior Offset The deviation of the first transition 0x000 to 0x001 compared to the ideal transition at 0 5 LSB Ideal value 0 LSB Figure 107 Offset Error Gain Error After adju...

Page 217: ...e width 1 LSB Ideal value 0 LSB Figure 110 Differential Non linearity DNL Quantization Error Due to the quantization of the input voltage into a finite number of codes a range of input voltages 1 LSB wide will code to the same value Always 0 5 LSB Absolute Accuracy The maximum deviation of an actual unadjusted transition compared to an ideal transition for any code This is the compound effect of O...

Page 218: ...ve input pin GAIN the selected gain factor and VREF the selected voltage reference The result is presented in two s complement form from 0x200 512d through 0x1FF 511d Note that if the user wants to perform a quick polarity check of the results it is sufficient to read the MSB of the result ADC9 in ADCH If the bit is one the result is negative and if the bit is zero the result is positive Figure 11...

Page 219: ... the ADC Data Register Write one to ADLAR to left adjust the result Otherwise the result is right adjusted Changing the ADLAR bit will affect the ADC Data Register immediately regardless of any ongoing conversions For a complete description of this bit see The ADC Data Register ADCL and ADCH on page 222 Table 83 Correlation Between Input Voltage and Output Codes VADCn Read Code Corresponding Decim...

Page 220: ...put Channel and Gain Selections MUX4 0 Single Ended Input Pos Differential Input Neg Differential Input Gain 00000 ADC0 00001 ADC1 00010 ADC2 00011 ADC3 N A 00100 ADC4 00101 ADC5 00110 ADC6 00111 ADC7 01000 ADC0 ADC0 10x 01001 ADC1 ADC0 10x 01010 ADC0 ADC0 200x 01011 ADC1 ADC0 200x 01100 ADC2 ADC2 10x 01101 ADC3 ADC2 10x 01110 ADC2 ADC2 200x 01111 ADC3 ADC2 200x 10000 ADC0 ADC1 1x 10001 ADC1 ADC1 ...

Page 221: ... trigger signal The trigger source is selected by setting the ADC Trigger Select bits ADTS in SFIOR Bit 4 ADIF ADC Interrupt Flag This bit is set when an ADC conversion completes and the Data Registers are updated The ADC Conversion Complete Interrupt is executed if the ADIE bit and the I bit in SREG are set ADIF is cleared by hardware when executing the corresponding interrupt handling vector Alt...

Page 222: ... from the registers If ADLAR is set the result is left adjusted If ADLAR is cleared default the result is right adjusted ADC9 0 ADC Conversion Result These bits represent the result from the conversion as detailed in ADC Conversion Result on page 218 Table 86 ADC Prescaler Selections ADPS2 ADPS1 ADPS0 Division Factor 0 0 0 2 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 16 1 0 1 32 1 1 0 64 1 1 1 128 Bit 15 14 13...

Page 223: ...in ADCSRA is set this will start a conversion Switching to Free Running mode ADTS 2 0 0 will not cause a trig ger event even if the ADC Interrupt Flag is set Bit 4 RES Reserved Bit This bit is reserved bit in the ATmega8535 and will always read as zero Bit 7 6 5 4 3 2 1 0 ADTS2 ADTS1 ADTS0 ACME PUD PSR2 PSR10 SFIOR Read Write R W R W R W R R W R W R W R W Initial Value 0 0 0 0 0 0 0 0 Table 87 ADC...

Page 224: ...fferent sections is configured by the BOOTSZ Fuses as shown in Table 93 on page 235 and Figure 113 These two sec tions can have different level of protection since they have different sets of Lock bits Application Section The Application section is the section of the Flash that is used for storing the application code The protection level for the Application section can be selected by the Applicat...

Page 225: ... NRWW section The RWW Section Busy bit RWWSB in the Store Program Memory Control Register SPMCR will be read as logical one as long as the RWW section is blocked for reading After a programming is completed the RWWSB must be cleared by software before reading code located in the RWW section See Store Program Memory Control Register SPMCR on page 228 for details on how to clear RWWSB NRWW No Read W...

Page 226: ...general Write Lock Lock Bit mode 2 does not control the program ming of the Flash memory by SPM instruction Similarly the general Read Write Lock Lock Bit mode 1 does not control reading nor writing by LPM SPM if it is attempted 0000 Flashend Program Memory BOOTSZ 11 Application Flash Section Boot Loader Flash Section Flashend Program Memory BOOTSZ 10 0000 Program Memory BOOTSZ 01 Program Memory B...

Page 227: ...to the Application section and LPM executing from the Boot Loader section is not allowed to read from the Application section If interrupt vectors are placed in the Boot Loader section interrupts are disabled while executing from the Application section 4 0 1 LPM executing from the Boot Loader section is not allowed to read from the Application section If interrupt vectors are placed in the Boot L...

Page 228: ...y with a page erase or a page write SPMEN is set If the RWWSRE bit is written while the Flash is being loaded the Flash load operation will abort and the data loaded will be lost Bit 3 BLBSET Boot Lock Bit Set If this bit is written to one at the same time as SPMEN the next SPM instruction within four clock cycles sets Boot Lock bits according to the data in R0 The data in R1 and the address in th...

Page 229: ... lower five bits will have no effect Addressing the Flash during Self Programming The Z pointer is used to address the SPM commands Since the Flash is organized in pages see Table 104 on page 241 the Program Counter can be treated as having two different sections One section consisting of the least significant bits is addressing the words within a page while the most significant bits are addressin...

Page 230: ...fer Perform a Page Write If only a part of the page needs to be changed the rest of the page must be stored for example in the temporary page buffer before the erase and then be rewritten When using alternative 1 the Boot Loader provides an effective Read Modify Write feature which allows the user software to first read the page do the necessary changes and then write back the modified data If alt...

Page 231: ... read during the Page Write Page Write to the NRWW section The CPU is halted during the operation Using the SPM Interrupt If the SPM interrupt is enabled the SPM interrupt will generate a constant interrupt when the SPMEN bit in SPMCR is cleared This means that the interrupt can be used instead of polling the SPMCR Register in software When using the SPM interrupt the Interrupt Vectors should be m...

Page 232: ...ts from software To read the Lock bits load the Z pointer with 0x0001 and set the BLBSET and SPMEN bits in SPMCR When an LPM instruction is executed within three CPU cycles after the BLBSET and SPMEN bits are set in SPMCR the value of the Lock bits will be loaded in the destination regis ter The BLBSET and SPMEN bits will auto clear upon completion of reading the Lock bits or if no LPM instruction...

Page 233: ...be completed provided that the power supply voltage is sufficient 3 Keep the AVR core in Power down Sleep mode during periods of low VCC This will prevent the CPU from attempting to decode and execute instructions effec tively protecting the SPMCR Register and thus the Flash from unintentional writes Programming Time for Flash When Using SPM The calibrated RC Oscillator is used to time Flash acces...

Page 234: ...tion ldi spmcrval 1 RWWSRE 1 SPMEN rcall Do_spm read back and check optional ldi looplo low PAGESIZEB init loop variable ldi loophi high PAGESIZEB not required for PAGESIZEB 256 subi YL low PAGESIZEB restore pointer sbci YH high PAGESIZEB Rdloop lpm r0 Z ld r1 Y cpse r0 r1 rjmp Error sbiw loophi looplo 1 use subi for PAGESIZEB 256 brne Rdloop return to RWW section verify that RWW section is safe t...

Page 235: ...ails about these two section see NRWW No Read While Write Section on page 225 and RWW Read While Write Section on page 225 Table 93 Boot Size Configuration 1 BOOTS Z1 BOOTS Z0 Boot Size Pages Appli cation Flash Section Boot Loader Flash Section End Appli cation Section Boot Reset Address Start Boot Loader Section 1 1 128 words 4 0x000 0xF7F 0xF80 0xFFF 0xF7F 0xF80 1 0 256 words 8 0x000 0xEFF 0xF00...

Page 236: ...nt bit in the Program Counter The Program Counter is 12 bits PC 11 0 PAGEMSB 4 Most significant bit which is used to address the words within one page 64 words in a page requires five bits PC 4 0 ZPCMSB Z12 Bit in Z register that is mapped to PCMSB Because Z0 is not used the ZPCMSB equals PCMSB 1 ZPAGEMSB Z5 Bit in Z register that is mapped to PCMSB Because Z0 is not used the ZPAGEMSB equals PAGEM...

Page 237: ...sh and EEPROM is disabled in Parallel and Serial Programming mode The Fuse bits are locked in both Serial and Parallel Programming mode 1 3 0 0 Further programming and verification of the Flash and EEPROM is disabled in Parallel and Serial Programming mode The Fuse bits are locked in both Serial and Parallel Programming mode 1 BLB0 Mode BLB02 BLB01 1 1 1 No restrictions for SPM or LPM accessing th...

Page 238: ... is not allowed to read from the Boot Loader section If interrupt vectors are placed in the Application section interrupts are disabled while executing from the Boot Loader section 4 0 1 LPM executing from the Application section is not allowed to read from the Boot Loader section If interrupt vectors are placed in the Application section interrupts are disabled while executing from the Boot Loade...

Page 239: ...ytes reside in a separate address space For the ATmega8535 the signature bytes are 1 0x000 0x1E indicates manufactured by Atmel 2 0x001 0x93 indicates 8 KB Flash memory 3 0x002 0x08 indicates ATmega8535 device when 0x001 is 0x93 Calibration Byte The ATmega8535 stores four different calibration values for the internal RC Oscillator These bytes resides in the signature row high byte of the addresses...

Page 240: ...e pulse The bit coding is shown in Table 102 When pulsing WR or OE the command loaded determines the action executed The dif ferent Commands are shown in Table 103 Figure 115 Parallel Programming Table 100 Pin Name Mapping Signal Name in Programming Mode Pin Name I O Function RDY BSY PD1 O 0 Device is busy programming 1 Device is ready for new command OE PD2 I Output Enable Active low WR PD3 I Wri...

Page 241: ...ble 103 Command Byte Bit Coding Command Byte Command Executed 1000 0000 Chip Erase 0100 0000 Write Fuse Bits 0010 0000 Write Lock Bits 0001 0000 Write Flash 0001 0001 Write EEPROM 0000 1000 Read Signature Bytes and Calibration byte 0000 0100 Read Fuse and Lock Bits 0000 0010 Read Flash 0000 0011 Read EEPROM Table 104 No of Words in a Page and no of Pages in the Flash Flash Size Page Size PCWORD No...

Page 242: ...rogramming mode with the original algorithm as described above Considerations for Efficient Programming The loaded command and address are retained in the device during programming For efficient programming the following should be considered The command needs only be loaded once when writing or reading multiple memory locations Skip writing the data value 0xFF that is the contents of the entire EE...

Page 243: ... BS1 to 1 This selects high data byte 2 Set XA1 XA0 to 01 This enables data loading 3 Set DATA Data high byte 0x00 0xFF 4 Give XTAL1 a positive pulse This loads the data byte E Latch Data 1 Set BS1 to 1 This selects high data byte 2 Give PAGEL a positive pulse This latches the data bytes See Figure 117 for signal waveforms F Repeat B through E until the entire buffer is filled or until all data wi...

Page 244: ...te sig nals are reset Figure 116 Addressing the Flash which is Organized in Pages 1 Note 1 PCPAGE and PCWORD are listed in Table 104 on page 241 Figure 117 Programming the Flash Waveforms 1 Note 1 XX is don t care The letters refer to the programming description above PROGRAM MEMORY WORD ADDRESS WITHIN A PAGE PAGE ADDRESS WITHIN THE FLASH INSTRUCTION WORD PAGE PCWORD PAGEMSB 0 00 01 02 PAGEEND PAG...

Page 245: ... is filled L Program EEPROM page 1 Set BS1 to 0 2 Give WR a negative pulse This starts programming of the EEPROM page RDY BSY goes low 3 Wait until to RDY BSY goes high before programming the next page See Figure 118 for signal waveforms Figure 118 Programming the EEPROM Waveforms Reading the Flash The algorithm for reading the Flash memory is as follows refer to Programming the Flash on page 243 ...

Page 246: ...C Load Data Low Byte Bit n 0 programs and bit n 1 erases the Fuse bit 3 Set BS1 to 0 and BS2 to 0 This selects low data byte 4 Give WR a negative pulse and wait for RDY BSY to go high Programming the Fuse High Bits The algorithm for programming the Fuse high bits is as follows refer to Programming the Flash on page 243 for details on Command and Data loading 1 A Load Command 0100 0000 2 C Load Dat...

Page 247: ...use High bits can now be read at DATA 0 means programmed 4 Set OE to 0 BS2 to 0 and BS1 to 1 The status of the Lock bits can now be read at DATA 0 means programmed 5 Set OE to 1 Figure 120 Mapping Between BS1 BS2 and the Fuse and Lock Bits During Read Reading the Signature Bytes The algorithm for reading the Signature bytes is as follows refer to Programming the Flash on page 243 for details on Co...

Page 248: ...ote 1 The timing requirements shown in Figure 121 i e tDVXH tXHXL and tXLDX also apply to loading operation Data Contol DATA XA0 1 BS1 BS2 XTAL1 tXHXL tWLWH tDVXH tXLDX tPLWL tWLRH WR RDY BSY PAGEL tPHPL tPLBX tBVPH tXLWL tWLBX tBVWL WLRL XTAL1 PAGEL tPLXH XLXH t tXLPH ADDR0 low byte DATA low byte DATA high byte ADDR1 low byte DATA BS1 XA0 XA1 LOAD ADDRESS LOW BYTE LOAD DATA LOW BYTE LOAD DATA HIG...

Page 249: ...ing Requirements 1 Note 1 The timing requirements shown in Figure 121 i e tDVXH tXHXL and tXLDX also apply to reading operation XTAL1 OE ADDR0 low byte DATA low byte DATA high byte ADDR1 low byte DATA BS1 XA0 XA1 LOAD ADDRESS LOW BYTE READ DATA LOW BYTE READ DATA HIGH BYTE LOAD ADDRESS LOW BYTE tBVDV tOLDV tXLOL tOHDZ ...

Page 250: ...ns tXLDX Data and Control Hold after XTAL1 Low 67 ns tXLWL XTAL1 Low to WR Low 0 ns tXLPH XTAL1 Low to PAGEL High 0 ns tPLXH PAGEL low to XTAL1 High 150 ns tBVPH BS1 Valid before PAGEL High 67 ns tPHPL PAGEL Pulse Width High 150 ns tPLBX BS1 Hold after PAGEL Low 67 ns tWLBX BS2 1 Hold after WR Low 67 ns tPLWL PAGEL Low to WR Low 67 ns tBVWL BS1 Valid to WR Low 67 ns tWLWH WR Pulse Width Low 150 ns...

Page 251: ... the XTAL1 pin 2 VCC 0 3 AVCC VCC 0 3 However AVCC should always be within 2 7 5 5V When programming the EEPROM an auto erase cycle is built into the self timed pro gramming operation in the Serial mode ONLY and there is no need to first execute the Chip Erase instruction The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into 0xFF Depending o...

Page 252: ... a given address The Program Memory Page is stored by loading the Write Program Memory Page instruction with the 8 MSB of the address If polling is not used the user must wait at least tWD_FLASH before issuing the next page See Table 108 Accessing the serial programming interface before the Flash write operation completes can result in incorrect programming 5 The EEPROM array is programmed one byt...

Page 253: ...s 0xFF in all locations programming of addresses that are meant to contain 0xFF can be skipped This does not apply if the EEPROM is reprogrammed without chip erasing the device In this case data polling cannot be used for the value 0xFF and the user will have to wait at least tWD_EEPROM before programming the next byte See Table 108 for tWD_EEPROM value Figure 125 Serial Programming Waveforms Tabl...

Page 254: ... EEPROM Memory 1010 0000 00xx xxxa bbbb bbbb oooo oooo Read data o from EEPROM memory at address a b Write EEPROM Memory 1100 0000 00xx xxxa bbbb bbbb iiii iiii Write data i to EEPROM memory at address a b Read Lock Bits 0101 1000 0000 0000 xxxx xxxx xxoo oooo Read Lock bits 0 programmed 1 unprogrammed See Table 96 on page 237 for details Write Lock Bits 1010 1100 111x xxxx xxxx xxxx 11ii iiii Wri...

Page 255: ...CC and GND Pins 200 0 PDIP og 400 mA TQFP MLF PLCCmA TA 40 C to 85 C VCC 2 7V to 5 5V unless otherwise noted Symbol Parameter Condition Min Typ Max Units VIL Input Low Voltage except XTAL1 and RESET pins VCC 2 7V 5 5V 0 5 0 2 VCC 1 V VIH Input High Voltage except XTAL1 and RESET pins VCC 2 7V 5 5V 0 6 VCC 2 VCC 0 5 V VIL1 Input Low Voltage XTAL1 pin VCC 2 7V 5 5V 0 5 0 1 VCC 1 V VIH1 Input High Vo...

Page 256: ...ugh each I O port can source more than the test conditions 20mA at VCC 5V 10mA at VCC 3V under steady state conditions non transient the following must be observed PDIP Package 1 The sum of all IOH for all ports should not exceed 200 mA 2 The sum of all IOH for port A0 A7 should not exceed 100 mA 3 The sum of all IOH for ports B0 B7 C0 C7 D0 D7 and XTAL2 should not exceed 100 mA PLCC MLF TQFP Pack...

Page 257: ...35 L 2502K AVR 10 06 If IOH exceeds the test condition VOH may exceed the related specification Pins are not guaranteed to source current greater than the listed test condition 5 Minimum VCC for Power down is 2 5V ...

Page 258: ...requency will vary with package type and board layout VIL1 VIH1 Table 110 External Clock Drive Symbol Parameter VCC 2 7V to 5 5V VCC 4 5V to 5 5V Units Min Max Min Max 1 tCLCL Oscillator Frequency 0 8 0 16 MHz tCLCL Clock Period 125 62 5 ns tCHCX High Time 50 25 ns tCLCX Low Time 50 25 ns tCLCH Rise Time 1 6 0 5 μs tCHCL Fall Time 1 6 0 5 μs ΔtCLCL Change in period from one clock cycle to the next...

Page 259: ...m VIHmin to VILmax 10 pF Cb 400 pF 3 20 0 1Cb 3 2 250 ns tSP 1 Spikes Suppressed by Input Filter 0 50 2 ns Ii Input Current each I O Pin 0 1VCC Vi 0 9VCC 10 10 µA Ci 1 Capacitance for each I O Pin 10 pF fSCL SCL Clock Frequency fCK 4 max 16fSCL 250kHz 5 0 400 kHz Rp Value of Pull up resistor fSCL 100 kHz fSCL 100 kHz tHD STA Hold Time Repeated START Condition fSCL 100 kHz 4 0 µs fSCL 100 kHz 0 6 µ...

Page 260: ...er than 6 MHz for the low time requirement to be strictly met at fSCL 100 kHz 7 The actual low period generated by the ATmega8535 Two wire Serial Interface is 1 fSCL 2 fCK thus the low time require ment will not be strictly met for fSCL 308 kHz when fCK 8 MHz Still ATmega8535 devices connected to the bus may communicate at full speed 400 kHz with other ATmega8535 devices as well as any other devic...

Page 261: ...ter 50 duty cycle 3 Rise Fall time Master 3 6 4 Setup Master 10 5 Hold Master 10 6 Out to SCK Master 5 tSCK 7 SCK to out Master 10 8 SCK to out high Master 10 9 SS low to out Slave 15 10 SCK period Slave 4 tck 11 SCK high low Slave 2 tck 12 Rise Fall time Slave 1 6 ns 13 Setup Slave 10 ns 14 Hold Slave 10 15 SCK to out Slave 15 16 SCK to SS high Slave 20 17 SS high to tri state Slave 10 18 SS low ...

Page 262: ...ments Master Mode Figure 129 SPI Interface Timing Requirements Slave Mode MOSI Data Output SCK CPOL 1 MISO Data Input SCK CPOL 0 SS MSB LSB LSB MSB 6 1 2 2 3 4 5 8 7 MISO Data Output SCK CPOL 1 MOSI Data Input SCK CPOL 0 SS MSB LSB LSB MSB 10 11 11 12 13 14 17 15 9 X 16 18 ...

Page 263: ...SB Single Ended Conversion VREF 4V VCC 4V ADC clock 1 MHz Noise Reduction mode 3 LSB Integral Non Linearity INL Single Ended Conversion VREF 4V VCC 4V ADC clock 200 kHz 0 75 LSB Differential Non Linearity DNL Single Ended Conversion VREF 4V VCC 4V ADC clock 200 kHz 0 25 LSB Gain Error Single Ended Conversion VREF 4V VCC 4V ADC clock 200 kHz 0 75 LSB Offset error Single Ended Conversion VREF 4V VCC...

Page 264: ...n 1x VREF 4V VCC 5V ADC clock 50 200 kHz 0 75 LSB Gain 10x VREF 4V VCC 5V ADC clock 50 200 kHz 0 75 LSB Gain 200x VREF 4V VCC 5V ADC clock 50 200 kHz 3 5 LSB Gain Error Gain 1x 1 7 Gain 10x 1 6 Gain 200x 0 3 Offset Error Gain 1x VREF 4V VCC 5V ADC clock 50 200 kHz 2 LSB Gain 10x VREF 4V VCC 5V ADC clock 50 200 kHz 2 5 LSB Gain 200x VREF 4V VCC 5V ADC clock 50 200 kHz 3 5 LSB Clock Frequency 50 200...

Page 265: ... for AVCC is 2 7V 3 Maximum for AVCC is 5 5V VINT Internal Voltage Reference 2 3 2 56 2 7 V RREF Reference Input Resistance 32 kΩ RAIN Analog Input Resistance 100 MΩ Table 115 ADC Characteristics Differential Channels Continued Symbol Parameter Condition Min 1 Typ 1 Max 1 Units ...

Page 266: ... operating voltage and frequency The current drawn from capacitive loaded pins may be estimated for one pin as CL VCC f where CL load capacitance VCC operating voltage and f average switch ing frequency of I O pin The parts are characterized at frequencies higher than test limits Parts are not guaran teed to function properly at frequencies higher than the ordering code indicates The difference be...

Page 267: ...urrent vs VCC Internal RC Oscillator 8 MHz ACTIVE SUPPLY CURRENT vs FREQUENCY 1 16 MHz 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 Frequency MHz I CC mA 5 5V 5 0V 4 5V 3 3V 3 0V 2 7V 4 0V ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 0 2 4 6 8 10 12 14 16 18 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ...

Page 268: ...Supply Current vs VCC Internal RC Oscillator 2 MHz ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 4 MHz 0 1 2 3 4 5 6 7 8 9 10 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ACTIVE SUPPLY CURRENT vs V INTERNAL RC OSCILLATOR 2 MHz 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 2 5 3 3 5 4 4 5 5 5 5 VCC V ICC mA 85 C 25 C 40 C CC ...

Page 269: ...ive Supply Current vs VCC 32 kHz External Oscillator ACTIVE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 0 0 5 1 1 5 2 2 5 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ACTIVE SUPPLY CURRENT vs VCC 32kHz EXTERNAL OSCILLATOR 0 0 01 0 02 0 03 0 04 0 05 0 06 0 07 0 08 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 25 C ...

Page 270: ...t vs Frequency 1 16 MHz IDLE SUPPLY CURRENT vs FREQUENCY 0 1 1 0 MHz 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5V 4 5V 4 0V 3 3V 3 0V 2 7V 5 0V IDLE SUPPLY CURRENT vs FREQUENCY 1 16 MHz 0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16 Frequency MHz I CC mA 5 5V 4 5V 4 0V 3 3V 3 0V 2 7V 5 0V ...

Page 271: ...upply Current vs VCC Internal RC Oscillator 4 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 8 MHz 0 1 2 3 4 5 6 7 8 9 10 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C IDLE SUPPLY CURRENT vs V CC INTERNAL RC OSCILLATOR 4 MHz 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ...

Page 272: ... Idle Supply Current vs VCC Internal RC Oscillator 1 MHz IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 2 MHz 0 0 5 1 1 5 2 2 5 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C IDLE SUPPLY CURRENT vs VCC INTERNAL RC OSCILLATOR 1 MHz 0 0 2 0 4 0 6 0 8 1 1 2 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ...

Page 273: ...re 144 Power Down Supply Current vs VCC Watchdog Timer Disabled IDLE SUPPLY CURRENT vs VCC 32kHz EXTERNAL OSCILLATOR 0 0 005 0 01 0 015 0 02 0 025 0 03 0 035 0 04 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 25 C POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 0 0 5 1 1 5 2 2 5 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C ...

Page 274: ...t Figure 146 Power Save Supply Current vs VCC Watchdog Timer Disabled POWER DOWN SUPPLY CURRENT vs VCC WATCHDOG TIMER ENABLED 0 0 005 0 01 0 015 0 02 0 025 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C POWER SAVE SUPPLY CURRENT vs VCC WATCHDOG TIMER DISABLED 0 2 4 6 8 10 12 14 16 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 25 C ...

Page 275: ...ure 148 Standby Supply Current vs VCC 1 MHz Resonator Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 455 kHz RESONATOR WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 70 80 90 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPLY CURRENT vs VCC 1 MHz RESONATOR WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 70 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 276: ...by Supply Current vs VCC 2 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 2 MHz RESONATOR WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 70 80 90 100 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPLY CURRENT vs VCC 2 MHz XTAL WATCHDOG TIMER DISABLED 0 10 20 30 40 50 60 70 80 90 100 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 277: ...2 Standby Supply Current vs VCC 4 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 4 MHz RESONATOR WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 140 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPLY CURRENT vs VCC 4 MHz XTAL WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 140 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 278: ...y Supply Current vs VCC 6 MHz Xtal Watchdog Timer Disabled STANDBY SUPPLY CURRENT vs VCC 6 MHz RESONATOR WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 140 160 180 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA STANDBY SUPPLY CURRENT vs VCC 6 MHz XTAL WATCHDOG TIMER DISABLED 0 20 40 60 80 100 120 140 160 180 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA ...

Page 279: ...156 I O Pin Pull up Resistor Current vs Input Voltage VCC 2 7V I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 5V 0 20 40 60 80 100 120 140 160 0 1 2 3 VOP V I OP uA 85 C 25 C 40 C I O PIN PULL UP RESISTOR CURRENT vs INPUT VOLTAGE Vcc 2 7V 0 10 20 30 40 50 60 70 80 0 0 5 1 1 5 2 2 5 3 VOP V I OP uA 85 C 25 C 40 C ...

Page 280: ...set Pull up Resistor Current vs Reset Pin Voltage VCC 2 7V RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 5V 0 20 40 60 80 100 120 0 1 2 3 VRESET V I RESET uA 85 C 25 C 40 C RESET PULL UP RESISTOR CURRENT vs RESET PIN VOLTAGE Vcc 2 7V 0 10 20 30 40 50 60 0 0 5 1 1 5 2 2 5 3 VRESET V I RESET uA 85 C 25 C 40 C ...

Page 281: ... 5V Figure 160 I O Pin Source Current vs Output Voltage VCC 2 7V I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 5V 0 10 20 30 40 50 60 70 80 90 2 5 3 3 5 4 4 5 5 5 5 VOH V I OH mA 85 C 25 C 40 C I O PIN SOURCE CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 5 10 15 20 25 30 0 0 5 1 1 5 2 2 5 3 VOH V I OH mA 85 C 25 C 40 C ...

Page 282: ...ure 162 I O Pin Sink Current vs Output Voltage VCC 2 7V I O PIN SINK CURRENT vs OUTPUT VOLTAGE Vcc 5V 0 10 20 30 40 50 60 70 80 90 0 0 5 1 1 5 2 2 5 VOL V I OL mA 85 C 25 C 40 C I O PIN SINK CURRENT vs OUTPUT VOLTAGE Vcc 2 7V 0 5 10 15 20 25 30 35 0 0 5 1 1 5 2 2 5 VOL V I OL mA 85 C 25 C 40 C ...

Page 283: ...1 Figure 164 I O Pin Input Threshold Voltage vs VCC VIL I O Pin Read As 0 I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 0 0 5 1 1 5 2 2 5 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C I O PIN INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C ...

Page 284: ...t Threshold Voltage vs VCC VIH Reset Pin Read As 1 I O PIN INPUT HYSTERESIS vs VCC 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C RESET INPUT THRESHOLD VOLTAGE vs VCC VIH IO PIN READ AS 1 0 0 5 1 1 5 2 2 5 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C ...

Page 285: ...ad As 0 Figure 168 Reset Input Pin Hysteresis vs VCC RESET INPUT THRESHOLD VOLTAGE vs VCC VIL IO PIN READ AS 0 0 5 1 1 5 2 2 5 3 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C RESET INPUT PIN HYSTERESIS vs VCC 0 0 1 0 2 0 3 0 4 0 5 0 6 2 5 3 3 5 4 4 5 5 5 5 VCC V Threshold V 85 C 25 C 40 C ...

Page 286: ...e BOD Level is 2 7V BOD THRESHOLDS vs TEMPERATURE BOD LEVEL IS 4 0 V 3 7 3 75 3 8 3 85 3 9 3 95 4 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising VCC Falling VCC BOD THRESHOLDS vs TEMPERATURE BOD LEVEL IS 2 7 V 2 5 2 55 2 6 2 65 2 7 2 75 2 8 2 85 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Temperature C Threshold V Rising VCC Falling VCC ...

Page 287: ...BANDGAP vs VCC 1 208 1 21 1 212 1 214 1 216 1 218 1 22 1 222 1 224 1 226 2 5 3 3 5 4 4 5 5 5 5 Vcc V Bandgap Voltage V 85 C 25 C 40 C ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Vcc 5V 0 006 0 005 0 004 0 003 0 002 0 001 0 0 001 0 002 0 0 5 1 1 5 2 2 5 3 3 5 4 4 5 5 Common Mode Voltage V Comparator Offset Voltage V 85 C 25 C 40 C ...

Page 288: ...Watchdog Oscillator Frequency vs VCC ANALOG COMPARATOR OFFSET VOLTAGE vs COMMON MODE VOLTAGE Vcc 2 7V 0 004 0 003 0 002 0 001 0 0 001 0 002 0 0 5 1 1 5 2 2 5 3 Common Mode Voltage V Comparator Offset Voltage V 85 C 25 C 40 C WATCHDOG OSCILLATOR FREQUENCY vs VCC 1000 1050 1100 1150 1200 1250 1300 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC kHz 85 C 25 C 40 C ...

Page 289: ...ted 8 MHz RC Oscillator Frequency vs VCC CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 6 6 5 7 7 5 8 8 5 9 50 30 10 10 30 50 70 90 110 Temp C F RC MHz 5 5V 2 7V 4 0V CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs VCC 6 5 6 7 6 9 7 1 7 3 7 5 7 7 7 9 8 1 8 3 8 5 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C ...

Page 290: ...illator Frequency vs Temperature CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 0 2 4 6 8 10 12 14 16 18 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 3 5 3 6 3 7 3 8 3 9 4 4 1 4 2 50 30 10 10 30 50 70 90 110 Temp C F RC MHz 5 5V 2 7V 4 0V ...

Page 291: ...scillator Frequency vs Osccal Value CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs VCC 3 4 3 5 3 6 3 7 3 8 3 9 4 4 1 4 2 2 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C CALIBRATED 4 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 0 1 2 3 4 5 6 7 8 9 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz ...

Page 292: ...MHz RC Oscillator Frequency vs VCC CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 1 75 1 8 1 85 1 9 1 95 2 2 05 2 1 50 30 10 10 30 50 70 90 110 Temp C F RC MHz 5 5V 2 7V 4 0V CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs VCC 1 7 1 75 1 8 1 85 1 9 1 95 2 2 05 2 1 2 15 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C ...

Page 293: ...tor Frequency vs Temperature CALIBRATED 2 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 0 0 5 1 1 5 2 2 5 3 3 5 4 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs TEMPERATURE 0 9 0 92 0 94 0 96 0 98 1 1 02 1 04 50 30 10 10 30 50 70 90 110 Temp C F RC MHz 5 5V 2 7V 4 0V ...

Page 294: ... vs Osccal Value CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs VCC 0 85 0 87 0 89 0 91 0 93 0 95 0 97 0 99 1 01 1 03 1 05 2 5 3 3 5 4 4 5 5 5 5 VCC V F RC MHz 85 C 25 C 40 C CALIBRATED 1 MHz RC OSCILLATOR FREQUENCY vs OSCCAL VALUE 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 OSCCAL VALUE F RC MHz ...

Page 295: ...wnout Detector Current vs VCC Figure 188 ADC Current vs VCC AREF AVCC BROWNOUT DETECTOR CURRENT vs VCC 0 0 005 0 01 0 015 0 02 0 025 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C ADC CURRENT vs VCC AREF AVCC 0 100 200 300 400 500 600 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C ...

Page 296: ...rent vs VCC Figure 190 Analog Comparator Current vs VCC AREF EXTERNAL REFERENCE CURRENT vs VCC 0 50 100 150 200 250 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C ANALOG COMPARATOR CURRENT vs VCC 0 20 40 60 80 100 120 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC uA 85 C 25 C 40 C ...

Page 297: ...s VCC 0 1 1 0 MHz Excluding Current Through The Reset Pull up PROGRAMMING CURRENT vs V 0 2 4 6 8 10 12 2 5 3 3 5 4 4 5 5 5 5 VCC V I CC mA 85 C 25 C 40 C CC RESET SUPPLY CURRENT vs VCC 0 1 1 0 MHz EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 0 5 1 1 5 2 2 5 3 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 1 Frequency MHz I CC mA 5 5V 5 0V 4 5V 3 3V 3 0V 2 7V 4 0V ...

Page 298: ...Figure 194 Reset Pulse Width vs VCC RESET SUPPLY CURRENT vs VCC 1 20 MHz EXCLUDING CURRENT THROUGH THE RESET PULLUP 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16 18 20 Frequency MHz I CC mA 5 5V 5 0V 4 5V 3 3V 3 0V 2 7V 4 0V RESET PULSE WIDTH vs VCC 0 200 400 600 800 1000 1200 2 5 3 3 5 4 4 5 5 5 5 VCC V Pulsewidth ns 85 C 25 C 40 C ...

Page 299: ...imer Counter2 Output Compare Register 131 0x22 0x42 ASSR AS2 TCN2UB OCR2UB TCR2UB 131 0x21 0x41 WDTCR WDCE WDE WDP2 WDP1 WDP0 42 0x20 1 0x40 1 UBRRH URSEL UBRR 11 8 169 UCSRC URSEL UMSEL UPM1 UPM0 USBS UCSZ1 UCSZ0 UCPOL 167 0x1F 0x3F EEARH EEAR8 19 0x1E 0x3E EEARL EEPROM Address Register Low Byte 19 0x1D 0x3D EEDR EEPROM Data Register 19 0x1C 0x3C EECR EERIE EEMWE EEWE EERE 19 0x1B 0x3B PORTA PORT...

Page 300: ... written 3 Some of the status flags are cleared by writing a logical one to them Note that the CBI and SBI instructions will operate on all bits in the I O Register writing a one back into any flag read as set thus clearing the flag The CBI and SBI instructions work with registers 0x00 to 0x1F only 0x00 0x20 TWBR Two wire Serial Interface Bit Rate Register 181 Register Summary Continued Address Na...

Page 301: ...outine Call PC PC k 1 None 3 ICALL Indirect Call to Z PC Z None 3 RET Subroutine Return PC STACK None 4 RETI Interrupt Return PC STACK I 4 CPSE Rd Rr Compare Skip if Equal if Rd Rr PC PC 2 or 3 None 1 2 3 CP Rd Rr Compare Rd Rr Z N V C H 1 CPC Rd Rr Compare with Carry Rd Rr C Z N V C H 1 CPI Rd K Compare Register with Immediate Rd K Z N V C H 1 SBRC Rr b Skip if Bit in Register Cleared if Rr b 0 P...

Page 302: ... Load Program Memory Rd Z None 3 LPM Rd Z Load Program Memory and Post Inc Rd Z Z Z 1 None 3 SPM Store Program Memory Z R1 R0 None IN Rd P In Port Rd P None 1 OUT P Rr Out Port P Rr None 1 PUSH Rr Push Register on Stack STACK Rr None 2 POP Rd Pop Register from Stack Rd STACK None 2 BIT AND BIT TEST INSTRUCTIONS SBI P b Set Bit in I O Register I O P b 1 None 2 CBI P b Clear Bit in I O Register I O ...

Page 303: ... AVR 10 06 SLEEP Sleep see specific descr for Sleep function None 1 WDR Watchdog Reset see specific descr for WDR Timer None 1 BREAK Break For On chip Debug Only None N A Mnemonics Operands Description Operation Flags Clocks ...

Page 304: ...ge 8 2 7 5 5V ATmega8535L 8AC ATmega8535L 8PC ATmega8535L 8JC ATmega8535L 8MC 44A 40P6 44J 44M1 Commercial 0 C to 70 C ATmega8535L 8AI ATmega8535L 8PI ATmega8535L 8JI ATmega8535L 8MI ATmega8535L 8AU 2 ATmega8535L 8PU 2 ATmega8535L 8JU 2 ATmega8535L 8MU 2 44A 40P6 44J 44M1 44A 40P6 44J 44M1 Industrial 40 C to 85 C 16 4 5 5 5V ATmega8535 16AC ATmega8535 16PC ATmega8535 16JC ATmega8535 16MC 44A 40P6 ...

Page 305: ...Thin 1 0 mm Plastic Gull Wing Quad Flat Package TQFP 40P6 40 pin 0 600 Wide Plastic Dual Inline Package PDIP 44J 44 lead Plastic J leaded Chip Carrier PLCC 44M1 A 44 pad 7 x 7 x 1 0 mm body lead pitch 0 50 mm Quad Flat No Lead Micro Lead Frame Package QFN MLF ...

Page 306: ...ENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE Notes 1 This package conforms to JEDEC reference MS 026 Variation ACB 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25 mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10 mm maximum A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 D 11 75 12 00 12 25 D1...

Page 307: ...0º 15º D e eB COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 4 826 A1 0 381 D 52 070 52 578 Note 2 E 15 240 15 875 E1 13 462 13 970 Note 2 B 0 356 0 559 B1 1 041 1 651 L 3 048 3 556 C 0 203 0 381 eB 15 494 17 526 e 2 540 TYP Notes 1 This package conforms to JEDEC reference MS 011 Variation AC 2 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion sha...

Page 308: ...ead coplanarity is 0 004 0 102 mm maximum A 4 191 4 572 A1 2 286 3 048 A2 0 508 D 17 399 17 653 D1 16 510 16 662 Note 2 E 17 399 17 653 E1 16 510 16 662 Note 2 D2 E2 14 986 16 002 B 0 660 0 813 B1 0 330 0 533 e 1 270 TYP COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE 1 14 0 045 X 45 PIN NO 1 IDENTIFIER 1 14 0 045 X 45 0 51 0 020 MAX 0 318 0 0125 0 191 0 0075 A2 45 MAX 3X A A1 B1 D2 E...

Page 309: ... 0 02 0 05 A3 0 25 REF b 0 18 0 23 0 30 D D2 5 00 5 20 5 40 6 90 7 00 7 10 6 90 7 00 7 10 E E2 5 00 5 20 5 40 e 0 50 BSC L 0 59 0 64 0 69 K 0 20 0 26 0 41 Note JEDEC Standard MO 220 Fig 1 SAW Singulation VKKD 3 TOP VIEW SIDE VIEW BOTTOM VIEW D E Marked Pin 1 ID E2 D2 b e Pin 1 Corner L A1 A3 A SEATING PLANE Pin 1 Triangle Pin 1 Chamfer C 0 30 Option A Option B Pin 1 Notch 0 20 R Option C K K 1 2 3...

Page 310: ...rising VCC the first Analog Comparator conver sion will take longer than expected on some devices Problem Fix Workaround When the device has been powered or reset disable then enable the Analog Com parator before the first conversion 2 Asynchronous Oscillator does not stop in Power down The asynchronous oscillator does not stop when entering Power down mode This leads to higher power consumption t...

Page 311: ... 29 Table 17 on page 42 and Table 111 on page 258 3 Updated Serial Peripheral Interface SPI on page 136 4 Updated note in Bit Rate Generator Unit on page 180 Changes from Rev 2502F 06 04 to Rev 2502G 04 05 1 Removed Preliminary and TBD s 2 Updated Table 37 on page 69 and Table 113 on page 261 3 Updated Electrical Characteristics on page 255 4 Updated Ordering Information on page 304 Changes from R...

Page 312: ... Figure 87 on page 191 Figure 98 on page 207 3 Added the section EEPROM Write During Power down Sleep Mode on page 22 4 Removed the references to the application notes Multi purpose Oscillator and 32 kHz Crystal Oscillator which do not exist 5 Updated code examples on page 44 6 Removed ADHSM bit 7 Renamed Port D pin ICP to ICP1 See Alternate Functions of Port D on page 64 8 Added information about...

Page 313: ...cteristics on page 263 14 Updated Register Summary on page 299 15 Various Timer 1 corrections 16 Added WD_FUSE period in Table 108 on page 253 Changes from Rev 2502A 06 02 to Rev 2502B 09 02 1 Canged the Endurance on the Flash to 10 000 Write Erase Cycles ...

Page 314: ...314 ATmega8535 L 2502K AVR 10 06 ...

Page 315: ...on Timing 13 Reset and Interrupt Handling 13 AVR ATmega8535 Memories 16 In System Reprogrammable Flash Program Memory 16 SRAM Data Memory 17 EEPROM Data Memory 18 I O Memory 23 System Clock and Clock Options 24 Clock Systems and their Distribution 24 Clock Sources 25 Default Clock Source 25 Crystal Oscillator 25 Low frequency Crystal Oscillator 28 External RC Oscillator 28 Calibrated Internal RC O...

Page 316: ...s 68 8 bit Timer Counter0 with PWM 71 Overview 71 Timer Counter Clock Sources 72 Counter Unit 72 Output Compare Unit 73 Compare Match Output Unit 75 Modes of Operation 76 Timer Counter Timing Diagrams 80 8 bit Timer Counter Register Description 83 Timer Counter0 and Timer Counter1 Prescalers 87 16 bit Timer Counter1 89 Overview 89 Accessing 16 bit Registers 92 Timer Counter Clock Sources 95 Counte...

Page 317: ... The USART Transmitter 152 Data Reception The USART Receiver 155 Asynchronous Data Reception 158 Multi processor Communication Mode 162 Accessing UBRRH UCSRC Registers 163 USART Register Description 164 Examples of Baud Rate Setting 170 Two wire Serial Interface 174 Features 174 Two wire Serial Interface Bus Definition 174 Data Transfer and Frame Format 175 Multi master Bus Systems Arbitration and...

Page 318: ... Programming the Flash 230 Memory Programming 237 Program And Data Memory Lock Bits 237 Fuse Bits 238 Signature Bytes 239 Calibration Byte 239 Parallel Programming Parameters Pin Mapping and Commands 240 Parallel Programming 242 Serial Downloading 251 Electrical Characteristics 255 Absolute Maximum Ratings 255 DC Characteristics 255 External Clock Drive Waveforms 258 External Clock Drive 258 Two w...

Page 319: ... 06 06 311 Changes from Rev 2502G 04 05 to Rev 2502H 04 06 311 Changes from Rev 2502F 06 04 to Rev 2502G 04 05 311 Changes from Rev 2502E 12 03 to Rev 2502G 06 04 311 Changes from Rev 2502E 12 03 to Rev 2502F 06 04 311 Changes from Rev 2502D 09 03 to Rev 2502E 12 03 311 Changes from Rev 2502C 04 03 to Rev 2502D 09 03 312 Changes from Rev 2502B 09 02 to Rev 2502C 04 03 312 Changes from Rev 2502A 06...

Page 320: ...vi ATmega8535 L 2502K AVR 10 06 ...

Page 321: ...Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH 1705 Fribourg Switzerland Tel 41 26 426 5555 Fax 41 26 426 5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721 9778 Fax 852 2722 1369 Japan 9F Tonetsu Shinkawa Bldg 1 24 8 Shinkawa Chuo ku Tokyo 104 0033 Japan Tel 81 3 3523 3551 Fax 81 3 3523 7581 ...

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