background image

4

2486AAS–AVR–02/2013

ATmega8(L)

The Atmel

®

AVR

®

 core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two inde-
pendent registers to be accessed in one single instruction executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.

The ATmega8 provides the following features: 8 Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 512 bytes of EEPROM, 1 Kbyte of SRAM, 23 general purpose
I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, a byte oriented Two-
wire Serial Interface, a 6-channel ADC (eight channels in TQFP and QFN/MLF packages) with
10-bit accuracy, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port,
and five software selectable power saving modes. The Idle mode stops the CPU while allowing
the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-
down mode saves the register contents but freezes the Oscillator, disabling all other chip func-
tions until the next Interrupt or Hardware Reset. In Power-save mode, the asynchronous timer
continues to run, allowing the user to maintain a timer base while the rest of the device is sleep-
ing. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous
timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the
crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very
fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
Flash Program memory can be reprogrammed In-System through an SPI serial interface, by a
conventional non-volatile memory programmer, or by an On-chip boot program running on the
AVR core. The boot program can use any interface to download the application program in the
Application Flash memory. Software in the Boot Flash Section will continue to run while the
Application Flash Section is updated, providing true Read-While-Write operation. By combining
an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel
ATmega8 is a powerful microcontroller that provides a highly-flexible and cost-effective solution
to many embedded control applications.

The ATmega8 is supported with a full suite of program and system development tools, including
C compilers, macro assemblers, program simulators, and evaluation kits.

Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Minimum and Maxi-
mum values will be available after the device is characterized.

Summary of Contents for ATmega8

Page 1: ... Compare Mode and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8 channel ADC in TQFP and QFN MLF package Eight Channels 10 bit Accuracy 6 channel ADC in PDIP package Six Channels 10 bit Accuracy Byte oriented Two wire Serial Interface Programmable Serial USART Master Slave SPI Serial Interface Programmable Watchdog Timer with Separate On chip Oscillator On chip Analog...

Page 2: ... T1 PD5 AIN0 PD6 AIN1 PD7 ICP1 PB0 PC5 ADC5 SCL PC4 ADC4 SDA PC3 ADC3 PC2 ADC2 PC1 ADC1 PC0 ADC0 GND AREF AVCC PB5 SCK PB4 MISO PB3 MOSI OC2 PB2 SS OC1B PB1 OC1A PDIP 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 MLF Top View INT1 PD3 XCK T0 PD4 GND VCC GND VCC XTAL1 TOSC1 PB6 XTAL2 TOSC2 PB7 PC1 ADC1 PC0 ADC0 ADC7 GND AREF ADC6 AVCC PB5 SCK T1 PD5 AIN0 PD6...

Page 3: ...ure 1 Block Diagram INTERNAL OSCILLATOR OSCILLATOR WATCHDOG TIMER MCU CTRL TIMING OSCILLATOR TIMERS COUNTERS INTERRUPT UNIT STACK POINTER EEPROM SRAM STATUS REGISTER USART PROGRAM COUNTER PROGRAM FLASH INSTRUCTION REGISTER INSTRUCTION DECODER PROGRAMMING LOGIC SPI ADC INTERFACE COMP INTERFACE PORTC DRIVERS BUFFERS PORTC DIGITAL INTERFACE GENERAL PURPOSE REGISTERS X Y Z ALU PORTB DRIVERS BUFFERS PO...

Page 4: ...the user to maintain a timer base while the rest of the device is sleep ing The ADC Noise Reduction mode stops the CPU and all I O modules except asynchronous timer and ADC to minimize switching noise during ADC conversions In Standby mode the crystal resonator Oscillator is running while the rest of the device is sleeping This allows very fast start up combined with low power consumption The devi...

Page 5: ...rce capability As inputs Port C pins that are externally pulled low will source current if the pull up resistors are activated The Port C pins are tri stated when a reset condition becomes active even if the clock is not running PC6 RESET If the RSTDISBL Fuse is programmed PC6 is used as an I O pin Note that the electrical char acteristics of PC6 differ from those of the other pins of Port C If th...

Page 6: ...Tmega8L 8AU ATmega8L 8AUR 3 ATmega8L 8PU ATmega8L 8MU ATmega8L 8MUR 3 32A 32A 28P3 32M1 A 32M1 A Industrial 40 C to 85 C 16 4 5 5 5 ATmega8 16AU ATmega8 16AUR 3 ATmega8 16PU ATmega8 16MU ATmega8 16MUR 3 32A 32A 28P3 32M1 A 32M1 A 8 2 7 5 5 ATmega8L 8AN ATmega8L 8ANR 3 ATmega8L 8PN ATmega8L 8MN ATmega8L 8MUR 3 32A 32A 28P3 32M1 A 32M1 A Industrial 40 C to 105 C 16 4 5 5 5 ATmega8 16AN ATmega8 16ANR...

Page 7: ...ms to JEDEC reference MS 026 Variation ABA 2 Dimensions D1 and E1 do not include mold protrusion Allowable protrusion is 0 25mm per side Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch 3 Lead coplanarity is 0 10mm maximum A 1 20 A1 0 05 0 15 A2 0 95 1 00 1 05 D 8 75 9 00 9 25 D1 6 90 7 00 7 10 Note 2 E 8 75 9 00 9 25 E1 6 90 7 00 7 10 Note 2 B 0 30 0 45 C 0 09...

Page 8: ...1 C L SEATING PLANE A 0º 15º D e eB B2 4 PLACES COMMON DIMENSIONS Unit of Measure mm SYMBOL MIN NOM MAX NOTE A 4 5724 A1 0 508 D 34 544 34 798 Note 1 E 7 620 8 255 E1 7 112 7 493 Note 1 B 0 381 0 533 B1 1 143 1 397 B2 0 762 1 143 L 3 175 3 429 C 0 203 0 356 eB 10 160 e 2 540 TYP Note 1 Dimensions D and E1 do not include mold Flash or Protrusion Mold Flash or Protrusion shall not exceed 0 25mm 0 01...

Page 9: ...of Measure mm SYMBOL MIN NOM MAX NOTE D1 D E1 E e b A3 A2 A1 A D2 E2 0 08 C L 1 2 3 P P 0 1 2 3 A 0 80 0 90 1 00 A1 0 02 0 05 A2 0 65 1 00 A3 0 20 REF b 0 18 0 23 0 30 D D1 D2 2 95 3 10 3 25 4 90 5 00 5 10 4 70 4 75 4 80 4 70 4 75 4 80 4 90 5 00 5 10 E E1 E2 2 95 3 10 3 25 e 0 50 BSC L 0 30 0 40 0 50 P 0 60 12o Note JEDEC Standard MO 220 Fig 2 Anvil Singulation VHHD 2 TOP VIEW SIDE VIEW BOTTOM VIE...

Page 10: ...Register TCNTx or asynchronous Output Compare Register OCRx 3 Signature may be Erased in Serial Programming Mode If the signature bytes are read before a chiperase command is completed the signature may be erased causing the device ID and calibration bytes to disappear This is critical espe cially if the part is running on internal RC oscillator Problem Fix Workaround Ensure that the chiperase com...

Page 11: ... or STS to set EERE bit triggers unexpected interrupt request Reading EEPROM by using the ST or STS command to set the EERE bit in the EECR reg ister triggers an unexpected EEPROM interrupt request Problem Fix Workaround Always use OUT or SBI to set EERE in EECR ...

Page 12: ...products EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT ...

Reviews: