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ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015
The ISP algorithm is controlled by the ATMISP software, which is running on the PC. The four JTAG
signals are generated and buffered by the ISP download cable before going into the ATF15xx device
on the CPLD Development/Programmer board. The 10-pin JTAG Port Header pinout on the CPLD
Development/Programmer board is shown in
Figure 8
, and the dimensions of this 10-pin male JTAG
header are shown in
Figure 9
.
Figure 8.
10-pin JTAG Port Header Pinout
Figure 9.
10-pin Male Header Dimensions
The 10-pin JTAG Port Header pinout is compatible with the ATDH1150USB and ATDH1150USB-K
USB based ISP cables as well as the ATDH1150PC/VPC and ByteBlaster/MV/II LPT port based ISP
cables. ATMISP v6.7 supports both the USB and LPT port based ISP cables while ATMISP v7.x and
later only supports the USB port based ISP cables.
Table 7.
Pin Numbers of JTAG Port Signals
44-pin TQFP
44-pin PLCC
84-pin PLCC
100-pin TQFP
TDI
1
7
14
4
TDO
32
38
71
73
TMS
7
13
23
15
TCK
26
32
62
62
GND
NC
NC
V
CC
GND
TDI
NC
TMS
TDO
TCK
10
8
6
4
2
9
7
5
3
1
10-Pin JTAG Port Header
(Top View)
0.100
0.025 Sq.
0.235
Top View
Side View
0.100
All dimensions are in inches.
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