ATF15xx-DK3-U Development/Programmer Kit [USER GUIDE]
Atmel-8961A-CPLD-ATF15xx-DK3-U-Development-Kit-UserGuide_072015
10
2MHz Oscillator and Clock Selection Jumper
The Clock Selection Jumper labeled JP-GCLK on the CPLD Development/Programmer Board is a
two-position jumper that allows the users to select which GCLK dedicated input pin (either GCLK1 or
GCLK2) of the ATF15xx device should be connected to the output of the 2MHz oscillator. In addition,
the jumper can be removed to allow an external clock source to be connected to GCLK1 and/or GCLK2
of the ATF15xx device.
Figure 6
is an illustration of the circuit diagram of the oscillator and selection
jumper.
Table 6
shows the pin numbers for the GCLK1 and GCLK2 dedicated input pins of the
ATF15xx device in all the different available package types.
Figure 6.
Circuit Diagram of Oscillator and Clock Selection Jumper
If GCLK1 jumper is set, the jumper will be located toward the side of the board. On the other
hand, if GCLK2 jumper is set, the jumper will be located toward the middle of the board.
Table 6.
Pin Numbers of GCLK1 and GCLK2
44-pin TQFP
44-pin PLCC
84-pin PLCC
100-pin TQFP
GCLK1
37
43
83
87
GCLK2
40
2
2
90
1
4
2
3
OSC
2MHZ
GCLK2
GCLK1
1
2
3
JPGCLK
R18
1K
R17
1K
VccOSC
C21
0.1uF
R39
100
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