5
6320B–ATARM–05-Nov-07
Application Note
4.
Error Detection and Correction
NAND Flash/SmartMedia devices contain by default invalid blocks which have one or more
invalid bits. Over the NAND Flash/SmartMedia lifetime, additional invalid blocks may occur
which can be detected/corrected by ECC code. To ensure data read/write integrity, system error
checking and correction (ECC) algorithms should be implemented. The AT91SAM9260/9263
and AT91SAM7SE microcontrollers provide ECC hardware support. The embedded ECC con-
troller is capable of single-bit error correction and 2-bit error detection per page
(528/1056/2112/4224). When NAND Flash/SmartMedia have more than 2 bits of errors, the data
cannot be corrected.
4.1
ECC Calculation Algorithm
For Single-bit Error Correction and Double bit Error Detection (SEC-DED) hsiao code is used.
32-bit ECC is generated in order to perform one bit correction per 512/1024/2048/4096 8- or 16-
bit words. Of the 32 ECC bits, 26 bits are for line parity and 6 bits are for column parity. They are
generated according to the schemes shown in
.
Figure 4-1.
Parity Generation for 512/1024/2048/4096 8-bit Words1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
P8'
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
P8'
P16
P16'
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
P8'
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
P8
P8'
P16
P16'
P32
P32
1st byte
P32
2nd byte
3rd byte
4 th byte
Page size th byte
(page size -1 )th byte
PX
PX'
Page size = 512 Px = 2048
Page size = 1024 Px = 4096
Page size = 2048 Px = 8192
Page size = 4096 Px = 16384
(page size -2 )th byte
(page size -3 )th byte
P1
P1'
P1'
P1
P1
P1'
P1'
P1
P2
P2'
P2
P2'
P4
P4'
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
