Atmel AT91 ARM Series Application Note Download | Manualshive

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6320B–ATARM–05-Nov-07

Application Note

Figure 4-2.

Parity Generation for 512/1024/2048/4096 16-bit Words

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Summary of Contents for AT91 ARM Series

Page 1: ...of bad blocks does not affect the good ones because each block is indepen dent and individually isolated from the bit lines by block select transistors Because NAND Flash devices have a finite lifetim...

Page 2: ...in Section 2 1 Internal Array Architecture NAND flash devices contain a certain percentage of invalid blocks at the end of the production process Invalid blocks are defined as blocks that contain one...

Page 3: ...Half Word 7thHalf Word 8thHalf Word BI LSN1 LSN0 LSN2 Reserved Reserved Reserved Reserved Reserved Reserved Reserved ECC0 ECC1 ECC2 S ECC0 S ECC1 Cell Array 512 Bytes Cell Array 512 Bytes Cell Array 5...

Page 4: ...8 bit devices or sixth half word 16 bit devices in the spare area of Small Page devices Manufacturers make sure that every invalid block has non FFh 8 bit devices or non FFFFh 16 bit devices data in...

Page 5: ...e bit correction per 512 1024 2048 4096 8 or 16 bit words Of the 32 ECC bits 26 bits are for line parity and 6 bits are for column parity They are generated according to the schemes shown in Figure 4...

Page 6: ...ARM 05 Nov 07 Application Note Figure 4 2 Parity Generation for 512 1024 2048 4096 16 bit Words 1st word 2nd word 3rd word 4th word Page size 3 th word Page size 2 th word Page size 1 th word Page siz...

Page 7: ...vice type is performed to NAND Flash or the SmartMedia device The ECC is refreshed at each write access of the page until the last byte or half word of the main area is written Once the whole main are...

Page 8: ...CLE 0 the ECC controller ignores any other command which is performed to the NAND Flash or the SmartMedia device The ECC controller performs error detection automatically by applying an XOR operation...

Page 9: ...d Sequence without Random Read Spare Area Main Area Size I Ox Address Read Command 1 Read Command 2 Address Cycles ECC Controller Reset Data Accesses Main Area Read Accesses Accesses allowing ECC calc...

Page 10: ...ytes ECC for 512 bytes of data per page The AT91SAM ECC controller manages ECC as 4 bytes ECC for 512 1024 2048 4096 bytes of data per page Since the ECC offset in the spare area and the number of ECC...

Page 11: ...05 Nov 07 Application Note 7 Revision History Doc Rev Comments Change Request Ref 6320A First issue 6320B Figure 4 3 and Figure 4 4 updated Section 3 2 Spare Area Assignment updated sentence refering...

Page 12: ...ELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIR...

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