Program Memory Lock Bits
The AT89C52 has three lock bits that can be left unpro-
grammed (U) or can be programmed (P) to obtain the ad-
ditional features listed in the following table.
When lock bit 1 is programmed, the logic level at the EA
pin is sampled and latched during reset. If the device is
powered up without a reset, the latch initializes to a ran-
dom value and holds that value until reset is activated. The
latched value of EA must agree with the current logic level
at that pin in order for the device to function properly.
Programming the Flash
The AT89C52 is normally shipped with the on-chip Flash
memory array in the erased state (that is, contents = FFH)
and ready to be programmed. The programming interface
accepts either a high-voltage (12-volt) or a low-voltage
(V
CC
) program enable signal. The low voltage program-
ming mode provides a convenient way to program the
AT89C52 inside the user’s system, while the high-voltage
programming mode is compatible with conventional third
party Flash or EPROM programmers.
The AT89C52 is shipped with either the high-voltage or
low-voltage programming mode enabled. The respective
top-side marking and device signature codes are listed in
the following table.
V
PP
= 12 V
V
PP
= 5 V
Top-Side Mark
AT89C52
AT89C52
xxxx
xxxx-5
yyww
yyww
Signature
(030H)=1EH
(030H)=1EH
(031H)=52H
(031H)=52H
(032H)=FFH
(032H)=05H
The AT89C52 code memory array is programmed byte-
by-byte in either programming mode.
To program any
non-blank byte in the on-chip Flash Memory, the entire
memory must be erased using the Chip Erase Mode.
Programming Algorithm: Before programming the
AT89C52, the address, data and control signals should be
set up according to the Flash programming mode table
and Figures 9 and 10. To program the AT89C52, take the
following steps.
1. Input the desired memory location on the address
lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/V
PP
to 12 V for the high-voltage program-
ming mode.
5. Pulse ALE/PROG once to program a byte in the Flash
array or the lock bits. The byte-write cycle is self-timed and
typically takes no more than 1.5 ms. Repeat steps 1
through 5, changing the address and data for the entire
array or until the end of the object file is reached.
Data Polling: The AT89C52 features Data Polling to indi-
cate the end of a write cycle. During a write cycle, an at-
tempted read of the last byte written will result in the com-
plement of the written data on PO.7. Once the write cycle
has been completed, true data is valid on all outputs, and
the next cycle may begin. Data Polling may begin any time
after a write cycle has been initiated.
Ready/Busy: The progress of byte programming can
also be monitored by the RDY/BSY output signal. P3.4 is
pulled low after ALE goes high during programming to in-
dicate BUSY. P3.4 is pulled high again when program-
ming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been
programmed, the programmed code data can be read
back via the address and data lines for verification. The
lock bits cannot be verified directly. Verification of the lock
(continued)
Lock Bit Protection Modes
Program Lock Bits
LB1
LB2
LB3
Protection Type
1
U
U
U
No program lock features.
2
P
U
U
MOVC instructions executed from external program memory are disabled from
fetching code bytes from internal memory, EA is sampled and latched on reset, and
further programming of the Flash memory is disabled.
3
P
P
U
Same as mode 2, but verify is also disabled.
4
P
P
P
Same as mode 3, but external execution is also disabled.
12
AT89C52