Atmel AT89C5132 Specification Sheet Download

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4173ES–USB–09/07

AT89C5132

Figure 4-2.

AT89C5132 84-pin PLCC

(1)

Note:

1. For development board only.

4.1

Signals

All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14.
Table 1. Ports Signal Description

PLCC84

P0.

P2.

/INT

.4/T

.5/T

P3.

/INT

P2.3/A11

P2.4/A12

P2.6/A14

P2.5/A13

P2.7/A15

MCLK

MDAT

MCMD

P0.

P5.

PAVSS

VSS

P3.

P4.

VSS

VDD

RST

SCLK

DSEL

DCLK

DOUT

.7/R

P1.0/KIN0

P1.1/KIN1

P1.2/KIN2

P1.3/KIN3

P1.4

P1.5

P1.7/SDA

FILT

PAVDD

VDD

P1.6/SCL

TST

P5.

P0.

P2.2/A10

ALE

ISP

P5.

P4.

UVDD

UVSS

P4.4

P4.5

VDD

VSS

D-

D+

P5.

Signal

Name

Type

Description

Alternate

Function

P0.7:0

I/O

Port 0

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
to them float and can be used as high impedance inputs. To avoid any parasitic
current consumption, floating P0 inputs must be polarized to V

or V

AD7:0

P1.7:0

I/O

Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

KIN3:0

SCL

SDA

Summary of Contents for AT89C5132

Page 1: ...erator Two Wire Master and Slave Modes Controller SPI Master and Slave Modes Controller Power Management Power on Reset Software Programmable MCU Clock Idle Mode Power down Mode Operating Conditions 3V 10 25 mA Typical Operating at 25 C Temperature Range 40 C to 85 C Packages TQFP80 PLCC84 Development Board Only Dice 1 Description The AT89C5132 is a mass storage device controlling data exchange be...

Page 2: ...Bytes Flash Interrupt Handler Unit FILT X2 X1 MMC Interface I O MDAT P0 P5 10 bit A to D Converter VSS VDD Keyboard Interface KIN3 0 I2 S PCM Audio Interface AVSS AVDD AIN1 0 Ports INT0 INT1 MOSI MISO Timers 0 1 T1 T0 SPI DataFlash Controller MCLK MCMD SCK RST AREF DSEL DCLK SCLK DOUT 64K Bytes USB Controller D D UART RXD TXD IDE Interface SS Watchdog Flash Boot 4K Bytes UVSS UVDD and BRG 1 1 1 1 ...

Page 3: ... AD0 PVSS VSS X2 X1 TST VSS 9 12 14 15 16 P4 3 SS P4 2 SCK P4 1 MOSI P4 0 MISO VSS VDD RST SCLK DSEL DCLK DOUT AIN1 AIN0 AREFN AREFP AVSS AVDD P3 7 RD P3 6 WR P3 5 T1 VDD P1 0 KIN0 P1 1 KIN1 P1 2 KIN2 P1 3 KIN3 P1 4 P1 5 P1 7 SDA FILT PVDD VDD P1 6 SCL 17 18 19 20 21 22 23 24 25 26 27 28 33 31 30 29 32 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 53 51 50 49 52 54 55 56 57 58 59 60 61 62 63 64 65 ...

Page 4: ... 66 70 5 6 7 8 9 P4 3 SS P4 2 SCK P4 1 MOSI P4 0 MISO VSS VDD RST SCLK DSEL DCLK DOUT AIN1 AIN0 AREFN AREFP AVSS AVDD VSS VDD P3 7 RD P3 0 RXD P1 0 KIN0 P1 1 KIN1 P1 2 KIN2 P1 3 KIN3 P1 4 P1 5 P1 7 SDA FILT PAVDD VDD P1 6 SCL 26 43 TST P5 2 P0 0 AD0 77 P2 2 A10 54 ALE ISP NC P5 1 P4 7 P4 6 76 75 10 11 28 27 29 30 31 32 UVDD UVSS 44 45 46 47 48 49 50 51 52 53 74 73 72 71 P4 4 P4 5 VDD VSS D D NC P5...

Page 5: ... chip inverting oscillator amplifier To use the internal oscillator a crystal resonator circuit is connected to this pin If an external oscillator is used leave X2 unconnected FILT I PLL Low Pass Filter input FILT receives the RC network of the PLL low pass filter Signal Name Type Description Alternate Function INT0 I Timer 0 Gate Input INT0 serves as external run control for timer 0 when selected...

Page 6: ... is the oversampling clock synchronized to the digital audio data DOUT and the channel selection signal DSEL Signal Name Type Description Alternate Function D I O USB Positive Data Upstream Port This pin requires an external 1 5 KΩ pull up to VDD for full speed operation D I O USB Negative Data Upstream Port Signal Name Type Description Alternate Function MCLK O MMC Clock output Data or command cl...

Page 7: ...put Slave Input Data Line When in master mode MOSI outputs data to the slave peripheral When in slave mode MOSI receives data from the master controller P4 1 SCK I O SPI Clock Line When in master mode SCK outputs clock to the slave peripheral When in slave mode SCK receives clock from the master controller P4 2 SS I SPI Slave Select Line When in controlled slave mode SS enables the slave mode P4 3...

Page 8: ...ternal latch is used to demultiplex the address from address data bus ISP I O ISP Enable Input This signal must be held to GND through a pull down resistor at the falling reset to force execution of the internal bootloader RD O Read Signal Read signal asserted during external data memory read operation P3 7 WR O Write Signal Write signal asserted during external data memory write operation P3 6 Si...

Page 9: ...rcuit Ground Connect these pins to ground AVDD PWR Analog Supply Voltage Connect this pin to 3V supply voltage AVSS GND Analog Ground Connect this pin to ground PVDD PWR PLL Supply voltage Connect this pin to 3V supply voltage PVSS GND PLL Circuit Ground Connect this pin to ground UVDD PWR USB Supply Voltage Connect this pin to 3V supply voltage UVSS GND USB Ground Connect this pin to ground ...

Page 10: ...bled P1 P2 and P3 transistors are disabled allowing pseudo open drain structure 3 In Port 2 P1 transistor is continuously driven when outputting a high level bit address A15 8 Circuit 1 Type Pins Input TST Input Output RST Input Output P1 2 P2 3 P3 P4 P53 0 Input Output P0 MCMD MDAT ISP PSEN Output ALE SCLK DCLK DOUT DSEL MCLK Input Output D D R TST VDD R RST VSS P VDD Watchdog Output P3 VSS N P1 ...

Page 11: ...only one voltage and allows in application software programming commonly known as IAP Hardware programming mode is also available using specific pro gramming tools 5 0 2 Boot Memory The AT89C5132 implements 4K Bytes of on chip boot memory provided in Flash technology This boot memory is delivered programmed with a standard bootloader software allowing in sys tem programming commonly known as ISP I...

Page 12: ...en operating as a Counter a Timer Counter counts negative transi tions on an external pin After a preset number of counts the Counter issues an interrupt request Watchdog Timer The AT8xC5132 implement a hardware Watchdog Timer that automatically resets the chip if it is allowed to time out The WDT provides a means of recovering from routines that do not complete successfully due to software or har...

Page 13: ... SPI supporting master and slave modes It is provided for the following purposes Remote control of the AT89C5132 by a host In System Programming Two wire Controller The AT89C5132 implements a 2 wire controller supporting the four standard master and slave modes with multimaster capability It is provided for the following purposes Connection of slave devices like LCD controller audio DAC Remote con...

Page 14: ...e Operating Conditions may affect device reliability Table 1 Digital DC Characteristics VDD 2 7 to 3 3V TA 40 to 85 C Symbol Parameter Min Typ 1 Max Units Test Conditions VIL Input Low Voltage 0 5 0 2 VDD 0 1 V VIH1 Input High Voltage except RST X1 0 2 VDD 1 1 VDD V VIH2 Input High Voltage RST X1 0 7 VDD 2 VDD 0 5 V VOL1 Output Low Voltage except P0 ALE MCMD MDAT MCLK SCLK DCLK DSEL DOUT 0 45 V IO...

Page 15: ...L Logical 1 to 0 Transition Current P1 P2 P3 P4 and P5 650 μA Vin 2 0 V RRST Pull Down Resistor 50 90 200 kΩ CIO Pin Capacitance 10 pF TA 25 C VRET VDD Data Retention Limit 1 8 V IDD Operating Current 3 X1 X2 mode 6 5 10 5 8 13 5 9 5 17 mA VDD 3 3 V 12 MHz 16 MHz 20 MHz IDL Idle Mode Current 3 X1 X2 mode 5 3 8 1 6 4 10 3 7 5 13 mA VDD 3 3 V 12 MHz 16 MHz 20 MHz IPD Power Down Mode Current 20 500 μ...

Page 16: ... UVSS AVSS RST MCMD P0 All other pins are unconnected VSS VDD TST MDAT VDD IPD VDD PVDD UVDD AVDD X2 VSS X1 NC VSS PVSS UVSS AVSS Symbol Parameter Min Typ Max Units Test Conditions AVDD Analog Supply Voltage 2 7 3 3 V AIDD Analog Operating Supply Current 600 μA AVDD 3 3V AIN1 0 0 to AVDD AIPD Analog Standby Current 2 μA AVDD 3 3V ADEN 0 or PD 1 AVIN Analog Input Voltage AVSS AVDD V AVREF Reference...

Page 17: ... not be used to drive other circuits 6 2 4 2 Parameters Table 3 Oscillator and Crystal Characteristics VDD 2 7 to 3 3V TA 40 to 85 C 6 2 5 Phase Lock Loop 6 2 5 1 Schematic Figure 6 5 PLL Filter Connection VSS X1 X2 Q C1 C2 Symbol Parameter Min Typ Max Unit CX1 Internal Capacitance X1 VSS 10 pF CX2 Internal Capacitance X2 VSS 10 pF CL Equivalent Load Capacitance X1 X2 5 pF DL Drive Level 50 μW F C...

Page 18: ...1 Schematic Figure 6 7 ISP Pull down Connection 6 2 7 2 Parameters Table 5 ISP Pull Down Characteristics VDD 3 to 3 3V TA 40 to 85 C Symbol Parameter Min Typ Max Unit R Filter Resistor 100 Ω C1 Filter Capacitance 1 10 nF C2 Filter Capacitance 2 2 2 nF D D VBUS GND D D VSS To Power RUSB RUSB VDD Supply RFS Symbol Parameter Min Typ Max Unit RUSB USB Termination Resistor 27 Ω RFS USB Full Speed Resis...

Page 19: ...lock X2 Mode Unit Min Max Min Max TCLCL Clock Period 50 50 ns TLHLL ALE Pulse Width 2 TCLCL 15 TCLCL 15 ns TAVLL Address Valid to ALE Low TCLCL 20 0 5 TCLCL 20 ns TLLAX Address hold after ALE Low TCLCL 20 0 5 TCLCL 20 ns TLLRL ALE Low to RD Low 3 TCLCL 30 1 5 TCLCL 30 ns TRLRH RD Pulse Width 6 TCLCL 25 3 TCLCL 25 ns TRHLH RD high to ALE High TCLCL 20 TCLCL 20 0 5 TCLCL 20 0 5 TCLCL 20 ns TAVDV Add...

Page 20: ...VLL Address Valid to ALE Low TCLCL 20 0 5 TCLCL 20 ns TLLAX Address hold after ALE Low TCLCL 20 0 5 TCLCL 20 ns TLLWL ALE Low to WR Low 3 TCLCL 30 1 5 TCLCL 30 ns TWLWH WR Pulse Width 6 TCLCL 25 3 TCLCL 25 ns TWHLH WR High to ALE High TCLCL 20 TCLCL 20 0 5 TCLCL 20 0 5 TCLCL 20 ns TAVWL Address Valid to WR Low 4 TCLCL 30 2 TCLCL 30 ns TQVWH Data Valid to WR High 7 TCLCL 20 3 5 TCLCL 20 ns TWHQX Da...

Page 21: ... Symbols Table 9 External IDE 16 bit Bus Cycles Timing Symbol Definitions 6 3 2 2 Timings Test conditions capacitive load on all pins 50 pF TWHLH TAVWL TLLAX TWHQX P2 P0 WR ALE TLHLL TWLWH A15 8 TAVLL TQVWH D7 0 Data Out TLLWL A7 0 Signals Conditions A Address H High D Data In L Low L ALE V Valid Q Data Out X No Longer Valid R RD Z Floating W WR ...

Page 22: ...ata In 9 TCLCL 65 4 5 TCLCL 65 ns TAVRL Address Valid to RD Low 4 TCLCL 30 2 TCLCL 30 ns TRLDV RD Low to Valid Data 5 TCLCL 30 2 5 TCLCL 30 ns TRLAZ RD Low to Address Float 0 0 ns TRHDX Data Hold After RD High 0 0 ns TRHDZ Instruction Float After RD High 2 TCLCL 25 TCLCL 25 ns Symbol Parameter Variable Clock Standard Mode Variable Clock X2 Mode Unit Min Max Min Max TCLCL Clock Period 50 50 ns TLHL...

Page 23: ...DAT16H SFR 6 3 3 SPI Interface 6 3 3 1 Definition of Symbols Table 12 SPI Interface Timing Symbol Definitions TAVDV TLLAX TRHDX TRHDZ TAVLL TAVRL P2 P0 RD ALE TLHLL TRLRH Data In TRLAZ TLLRL TRHLH TRLDV D7 0 A7 0 Data In D15 81 A15 8 TWHLH TAVWL TLLAX TWHQX P2 P0 WR ALE TLHLL TWLWH TAVLL TQVWH D7 0 Data Out TLLWL A7 0 D15 81 Data Out A15 8 Signals Conditions C Clock H High I Data In L Low O Data O...

Page 24: ...SH TCHSH SS High after Clock Edge 0 ns TIVCL TIVCH Input Data Valid to Clock Edge 100 ns TCLIX TCHIX Input Data Hold after Clock Edge 100 ns TSLOV SS Low to Output Data Valid 130 ns TSHOX Output Data Hold after SS High 130 ns TSHSL SS High to SS Low 1 TILIH Input Rise Time 2 μs TIHIL Input Fall Time 2 μs TOLOH Output Rise Time 100 ns TOHOL Output Fall Time 100 ns Master Mode TCHCH Clock Period 4 T...

Page 25: ...h has just been received TSLCL TSLCH TCHCL TCLCH MOSI input SCK SSCPOL 0 input SS input SCK SSCPOL 1 input MISO output TCHCH TCLCX TCHCX TIVCL TCLIX TCHIX TIVCH TCHOV TCLOV TCHOX TCLOX MSB IN BIT 6 LSB IN SLAVE MSB OUT SLAVE LSB OUT BIT 6 TSLOV 1 TSHOX TSHSL TCHSH TCLSH SI input SCK SSCPOL 0 output SS1 output SCK SSCPOL 1 output SO output TCHCH TCLCX TCHCX TIVCL TCLIX TCHIX TIVCH TCHOV TCLOV TCHOX...

Page 26: ... 17 TWI Interface AC Timing TCHCL TCLCH MOSI input SCK SSCPOL 0 input SS1 input SCK SSCPOL 1 input MISO output TCHCH TCLCX TCHCX TIVCL TCLIX TCHIX TIVCH TCLOV TCHOV TCLOX TCHOX MSB IN BIT 6 LSB IN SLAVE MSB OUT SLAVE LSB OUT BIT 6 TSLOV 1 TSHOX TSHSL TCHSH TCLSH TSLCL TSLCH SI input SCK SSCPOL 0 output SS1 output SCK SSCPOL 1 output SO output TCHCH TCLCX TCHCX TIVCL TCLIX TCHIX TIVCH TCHOV TCLOV T...

Page 27: ...TLOW SCL low time 16 TCLCL 4 4 7 μs 1 THIGH SCL high time 14 TCLCL 4 4 0 μs 1 TRC SCL rise time 1 μs 2 TFC SCL fall time 0 3 μs 0 3 μs 3 TSU DAT1 Data set up time 250 ns 20 TCLCL 4 TRD TSU DAT2 SDA set up time before repeated START condition 250 ns 1 μs 1 TSU DAT3 SDA set up time before STOP condition 250 ns 8 TCLCL 4 THD DAT Data hold time 0 ns 8 TCLCL 4 TFC TSU STA Repeated START set up time 14 ...

Page 28: ...lock H High D Data In L Low O Data Out V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 50 ns TCHCX Clock High Time 10 ns TCLCX Clock Low Time 10 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TDVCH Input Data Valid to Clock High 3 ns TCHDX Input Data Hold after Clock High 3 ns TCHOX Output Data Hold after Clock High 5 ns TOVCH Output Data Valid to Clock High ...

Page 29: ...6 3 6 3 Waveforms Figure 6 18 Audio Interface Waveforms Signals Conditions C Clock H High O Data Out L Low S Data Select V Valid X No Longer Valid Symbol Parameter Min Max Unit TCHCH Clock Period 325 5 1 ns TCHCX Clock High Time 30 ns TCLCX Clock Low Time 30 ns TCLCH Clock Rise Time 10 ns TCHCL Clock Fall Time 10 ns TCLSV Clock Low to Select Valid 10 ns TCLOV Clock Low to Data Valid 10 ns DCLK TCH...

Page 30: ...of gain and offset errors see Figure 6 20 4 The offset error is the absolute difference between the straight line which fits the actual trans fer curve after removing of gain error and the straight line which fits the ideal transfer curve see Figure 6 20 5 The gain error is the relative difference in percent between the straight line which fits the actual transfer curve after removing of offset er...

Page 31: ...stics ADEN Bit ADSST Bit TEHSH TSHSL CLK TCLCL 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 Offset Error Code Out AVIN LSBideal OSe Offset Error OSe Gain Error Ge Ideal Transfer Curve 1 LSB Ideal Integral Non linearity ILe Differential Non linearity DLe Center of a Step Example of an Actual Transfer Curve 0 0 ...

Page 32: ...ory Internal Busy Waveforms 6 3 9 External Clock Drive and Logic Level References 6 3 9 1 Definition of Symbols Table 21 External Clock Timing Symbol Definitions Signals Conditions S ISP L Low R RST V Valid B FBUSY flag X No Longer Valid Symbol Parameter Min Typ Max Unit TSVRL Input ISP Valid to RST Edge 50 ns TRLSX Input ISP Hold after RST Edge 50 ns TBHBL FLASH Internal Busy Programming Time 10 ...

Page 33: ... logic 0 Figure 6 25 Float Waveforms Note For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH VOL level occurs with IOL IOH 20 mA Symbol Parameter Min Max Unit TCLCL Clock Period 50 ns TCHCX High Time 10 ns TCLCX Low Time 10 ns TCLCH Rise Time 3 ns TCHCL Fall Time 3 ns TCR Cyclic Ratio in X...

Page 34: ...r development board Possible Order Entries 1 Part Number Memory Size Bytes Supply Voltage Temperature Range Max Frequency MHz Package Packing Product Marking AT89C5132 ROTIL 64K Flash 3V Industrial 40 TQFP80 Tray 895132 IL AT89C5132 ROTUL 64K Flash 3V Industrial Green 40 TQFP80 Tray 895132 UL ...

Page 35: ...35 4173ES USB 09 07 AT89C5132 8 Package Information 8 1 TQFP80 ...

Page 36: ...36 4173ES USB 09 07 AT89C5132 8 2 PLCC84 ...

Page 37: ...connection schematic in USB section 2 Add USB termination characteristics in DC Characteristics section 3 Page access mode clarification in Data Memory section 9 3 Changes from 4173C 07 04 4173D 01 05 1 Interrupt priority number clarification to match number defined by development tools 9 4 Changes from to 4317D 01 05 to 4173E 09 07 1 Added green product ordering information 2 Removed Preliminary ...

Page 38: ...dot herwise Atmel products are not suitable for and shall not be used in automotive applications Atmel s products are not intended authorized or warranted for use as compo nents in applications intended to support or sustain life Atmel Corporation Atmel Operations 2325 Orchard Parkway San Jose CA 95131 USA Tel 1 408 441 0311 Fax 1 408 487 2600 Regional Headquarters Europe Atmel Sarl Route des Arse...

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