790
32072H–AVR32–10/2012
AT32UC3A3
29. Analog-to-Digital Converter (ADC)
Rev: 2.0.0.1
29.1
Features
•
Integrated multiplexer offering up to eight independent analog inputs
•
Individual enable and disable of each channel
•
Hardware or software trigger
– External trigger pin
– Timer counter
outputs (corresponding TIOA
trigger)
•
Peripheral DMA Controller support
•
Possibility of ADC timings configuration
•
Sleep mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all enabled
channels
29.2
Overview
The Analog-to-Digital Converter (ADC) is based on a Successive Approximation Register (SAR)
10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital
conversions of 8
analog lines. The conversions extend from 0V to VDDANA.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on rising edge of the TRIGGER pin, or internal triggers from timer counter out-
put(s) are configurable.
The ADC also integrates a sleep mode and a conversion sequencer and connects with a Periph-
eral DMA Controller channel. These features reduce both power consumption and processor
intervention.
Finally, the user can configure ADC timings, such as startup time and sample & hold time.
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
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Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
