582
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-42. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 25-43. SPI Transfer Format (CPHA=0, 8 bits per transfer)
25.6.15.4
Receiver and Transmitter Control
”Manchester Encoder” on page 583
, and
.
25.6.15.5
Character Transmission and Reception
In SPI master mode, the slave select line (NSS) is asserted low one bit period before the start of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
CLK cycle (for reference)
CLK
(CPOL= 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
MSB
1
CLK
(CPOL= 0)
3
5
6
7
8
LSB
1
2
3
4
6
6
5
5
4
3
2
1
LSB
2
4
CLK cycle (for reference)
CLK
(CPOL= 0)
CLK
(CPOL= 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB
6
5
MSB
6
5
4
4
3
3
2
2
1
1
LSB
LSB
8
7
6
5
4
3
2
1
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
