567
32072H–AVR32–10/2012
AT32UC3A3
25.6.9.1
IrDA Modulation
The RZI modulation scheme is used, where a zero is represented by a light pulse 3/16 of a bit
period, and no pulse to represent a one. Some examples of signal pulse duration are shown in
shows an example of character transmission.
Figure 25-25. IrDA Modulation
25.6.9.2
IrDA Baud Rate
As the IrDA mode shares some logic with the ISO7816 mode, the FIDI.FI_DI_RATIO field must
be configured correctly.
See Section “25.6.16” on page 583.
shows some examples
of BRGR.CD values, baud rate error, and pulse duration. Note that the maximal acceptable error
rate of ±1.87% must be met.
Table 25-12. IrDA Pulse Duration
Baud Rate
Pulse Duration (3/16)
2.4 Kbit/s
78.13 µs
9.6 Kbit/s
19.53 µs
19.2 Kbit/s
9.77 µs
38.4 Kbit/s
4.88 µs
57.6 Kbit/s
3.26 µs
115.2 Kbit/s
1.63 µs
Bit Period
Bit Period
3
16
Start
Bit
Data Bits
Stop
Bit
0
0
0
0
0
1
1
1
1
1
Transmitter
Output
TXD
Table 25-13. IrDA Baud Rate Error
Peripheral Clock
Baud Rate
CD
Baud Rate Error
Pulse Time
3 686 400
115 200
2
0.00%
1.63
20 000 000
115 200
11
1.38%
1.63
32 768 000
115 200
18
1.25%
1.63
40 000 000
115 200
22
1.38%
1.63
3 686 400
57 600
4
0.00%
3.26
20 000 000
57 600
22
1.38%
3.26
32 768 000
57 600
36
1.25%
3.26
40 000 000
57 600
43
0.93%
3.26
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...