346
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address
19.11 Disabling a Channel Prior to Transfer Completion
Under normal operation, software enables a channel by writing a ‘1’ to the Channel Enable Reg-
ister, ChEnReg.CH_EN, and hardware disables a channel on transfer completion by clearing the
ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Configuration Register
(CFGx) register.
1.
If software wishes to disable a channel prior to the DMA transfer completion, then it can
set the CFGx.CH_SUSP bit to tell the DMACA to halt all transfers from the source
peripheral. Therefore, the channel FIFO receives no new data.
2.
Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel
FIFO is empty.
Channel Enabled by
software
LLI Fetch
Hardware reprograms
SARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Is DMAC in
Row 1 of Table 4 ?
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here
yes
no
Summary of Contents for AT32UC3A3128
Page 61: ...61 32072H AVR32 10 2012 AT32UC3A3 PLLEN PLL Enable 0 PLL is disabled 1 PLL is enabled...
Page 592: ...592 32072H AVR32 10 2012 AT32UC3A3 Manchester Configuration Register on page 614...
Page 989: ...989 32072H AVR32 10 2012 AT32UC3A3 37 2 Package Drawings Figure 37 1 TFBGA 144 package drawing...
Page 991: ...991 32072H AVR32 10 2012 AT32UC3A3 Figure 37 3 VFBGA 100 package drawing...
