Asus PRL-DLS533, User Manual

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1-8 Chapter 1: Product introduction
604-pin CPU sockets. A 604-pin surface mount, Zero Insertion
Force (ZIF) socket for the Intel
®
Xeon™ processor with 512KB L2
cache and a 533MHz or a 400MHz system bus that allows up to
4.2GB/s or 3.2GB/s data transfer rate.
8-pin 12V SSI power connector. This power connector is for an
ATX power supply.
24/20-pin ATX power connector. This power connector is for an
ATX power supply.
ServerWorks
®
Grand Champion SuperLite north bridge CMIC-
SL. The Champion Memory and I/O Controller SuperLite (CMIC-
SL) acts as the host bridge of the Grand Champion SuperLite
(GCSL) SystemSet. The GCSL device interfaces directly to the
processor bus, and integrates the functions of the main memory
controller and the Inter Module Bus (IMB) interface unit. The
processor interface supports a 533MHz Front Side Bus (FSB)
providing a 4.2GB/s bandwidth, memory bandwidth with up to 4GB
registered ECC PC2100/1600 DDR DIMMs, and two high speed
IMBs plus one thin IMB to connect to the south bridge CSB6.
DIP switches. This 5-switch Dual Inline Package (DIP) allows you
to set the CPU external frequency.
DDR DIMM sockets. These four 184-pin DIMM sockets support up to
4GB system memory using registered ECC PC2100/1600 DDR DIMMs.
Floppy disk connector. This connector accommodates the provided
ribbon cable for the floppy disk drive. One side of the connector is
slotted to prevent incorrect insertion of the floppy disk cable.
ServerWorks
®
South Bridge, CSB6 performs as a PCI to LPC
(Low Pin Count) Bridge and integrates PCI master/slave functions,
DMA controller, ATA100 IDE interface, USB contoller, SMBus host,
ACPI and other integral functions.
IDE connectors. These dual-channel bus master IDE connectors
support up to four Ultra DMA/100/66, PIO Modes 3 & 4 IDE
devices. Both the primary (blue) and secondary (blue) connectors
are slotted to prevent incorrect insertion of the IDE ribbon cable.
Third IDE (black) with PIO mode 3/4 support provides more device
connectivity in this server system.
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1.4.2 Core specifications