Asus P552W, Manual

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The first GPS debug process is GPS DC debug. The purpose of
this process is to ensure that GPS chip (U2001) is supplied proper
voltage levels and reference clocks. Besides, digital data transmission
between GPS chip and CPLD is another important checking point. In
the beginning of OS booting, CPLD transmits digital data to GPS chip
via UART interface. If GPS chip does not receive data from CPL D,
GPS function can not work normally. Moreover, engineers need a
debug tool, also called as GPSinformation_en, to enforce GPS chip
into test mode and then all power supplies and reference clocks,
TCXO and RTC, are enable. Under GPS test mode, power domain,
including LDO, power switch, and four voltage regulators of U2001
can be measured by a multimeter. In addition, GPS on/off trigger
mechanism and two clocks, TCXO and RTC, can be measured by an
oscilloscope.
The detail steps of GPS DC debug are listed as follows.
a. Use an oscilloscope to probe R1750 because CPLD transmit
data while OS booting. CPLD needs to be replaced if no data is
measured on R1750. The following figure is an example showing
data from CPLD.
●
R1750