Chapter 3
–
AMI BIOS Setup
92
EPIC
Bo
ar
d
EPIC
-T
G
H
7
Data Bits
7
8
Optimal Default, Failsafe Default
Parity
None
Optimal Default, Failsafe Default
Even
Odd
Mark
Space
A parity bit can be sent with the data bits to detect some transmission errors. Even:
parity bit is 0 if the num of 1's in the data bits is even. Odd: parity bit is 0 if num of 1's in
the data bits is odd. Mark: parity bit is always 1. Space: Parity bit is always 0. Mark and
Space Parity do not allow for error detection. They can be used as an additional data
bit.
Stop Bits
1
Optimal Default, Failsafe Default
2
Stop bits indicate the end of a serial data packet. (A start bit indicates the beginning).
The standard setting is 1 stop bit. Communication with slow devices may require more
than 1 stop bit.
Flow Control
None
Optimal Default, Failsafe Default
Hardware RTS/CTS
Flow control can prevent data loss from buffer overflow. When sending data, if the
receiving buffers are full, a 'stop' signal can be sent to stop the data flow. Once the
buffers are empty, a 'start' signal can be sent to re-start the flow. Hardware flow control
uses two wires to send start/stop signals.
VT-UTF8 Combo
Key Support
Disabled
Enabled
Optimal Default, Failsafe Default
Enable VT-UTF8 Combination Key Support for ANSI/VT100 terminals.
Recorder Mode
Disabled
Optimal Default, Failsafe Default
Enabled
With this mode enabled only text will be sent. This is to capture Terminal data.
Resolution 100x31 Disabled
Optimal Default, Failsafe Default
Enabled
Enables or disables extended terminal resolution.
Putty KeyPad
VT100
Optimal Default, Failsafe Default
LINUX
XTERMR6
SCO
ESCN
VT400
Select FunctionKey and KeyPad on Putty.
Summary of Contents for AAEON EPIC-TGH7
Page 1: ...Last Updated August 8 2022 EPIC TGH7 EPIC Board User s Manual 1st Ed ...
Page 15: ...EPIC Board EPIC TGH7 Chapter 1 Chapter 1 Product Specifications ...
Page 19: ...EPIC Board EPIC TGH7 Chapter 2 Chapter 2 Hardware Information ...
Page 20: ...Chapter 2 Hardware Information 6 EPIC Board EPIC TGH7 2 1 Dimensions Component Side ...
Page 21: ...Chapter 2 Hardware Information 7 EPIC Board EPIC TGH7 Solder Side ...
Page 23: ...Chapter 2 Hardware Information 9 EPIC Board EPIC TGH7 Solder Side ...
Page 24: ...Chapter 2 Hardware Information 10 EPIC Board EPIC TGH7 2 3 Block Diagram ...
Page 63: ...EPIC Board EPIC TGH7 Chapter 3 Chapter 3 AMI BIOS Setup ...
Page 66: ...Chapter 3 AMI BIOS Setup 52 EPIC Board EPIC TGH7 3 3 Setup Submenu Main ...
Page 67: ...Chapter 3 AMI BIOS Setup 53 EPIC Board EPIC TGH7 3 4 Setup Submenu Advanced ...
Page 69: ...Chapter 3 AMI BIOS Setup 55 EPIC Board EPIC TGH7 3 4 2 Memory Configuration ...
Page 74: ...Chapter 3 AMI BIOS Setup 60 EPIC Board EPIC TGH7 3 4 5 PCH FW Configuration ...
Page 76: ...Chapter 3 AMI BIOS Setup 62 EPIC Board EPIC TGH7 3 4 7 NVMe Configuration ...
Page 97: ...Chapter 3 AMI BIOS Setup 83 EPIC Board EPIC TGH7 3 6 5 Legacy Logical Devices Configuration ...
Page 117: ...Chapter 3 AMI BIOS Setup 103 EPIC Board EPIC TGH7 3 8 1 BBS Priorities ...
Page 118: ...Chapter 3 AMI BIOS Setup 104 EPIC Board EPIC TGH7 3 9 Setup Submenu Save Exit ...
Page 119: ...EPIC Board EPIC TGH7 Chapter 4 Chapter 4 Drivers Installation ...
Page 122: ...EPIC Board EPIC TGH7 Appendix A Appendix A I O Information ...
Page 123: ...Appendix A I O Information 109 EPIC Board EPIC TGH7 A 1 I O Address Map ...
Page 124: ...Appendix A I O Information 110 EPIC Board EPIC TGH7 A 2 Memory Address Map ...
Page 125: ...Appendix A I O Information 111 EPIC Board EPIC TGH7 A 3 IRQ Mapping Chart ...
Page 126: ...Appendix A I O Information 112 EPIC Board EPIC TGH7 ...
Page 127: ...Appendix A I O Information 113 EPIC Board EPIC TGH7 ...
Page 128: ...EPIC Board EPIC TGH7 Appendix B Appendix B Mating Connectors ...
Page 131: ...EPIC Board EPIC TGH7 Appendix C Appendix C 3 Pin ATX Behavior Description ...