English
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Write to Read Delay (tWTR_S)
The number of clocks between the last valid write operation and the next read command to
the same internal bank.
Read to Precharge (tRTP)
The number of clocks that are inserted between a read command to a row pre-
charge command to the same rank.
Four Activate Window (tFAW)
The time window in which four activates are allowed the same rank.
CAS Write Latency (tCWL)
Configure CAS Write Latency.
Third Timing
tREFI
Configure refresh cycles at an average periodic interval.
tCKE
Configure the period of time the DDR4 initiates a minimum of one refresh
command internally once it enters Self-Refresh mode.
Turn Around Timing
tRDRD_sg
Configure between module read to read delay.
tRDRD_dg
Configure between module read to read delay.
tRDRD_dr
Configure between module read to read delay.
tRDRD_dd
Configure between module read to read delay.
tRDWR_sg
Configure between module read to write delay.
Summary of Contents for Z490 AQUA
Page 1: ......
Page 27: ...English 20 1 2 1 Removing the Water cooling Module Removing the CPU Backplate...
Page 30: ...English 23 Z490 AQUA Screw Assembly Schematic Front View 1 1 1 1 1 1...
Page 35: ...English 28 4 5 3...
Page 38: ...English 31 Z490 AQUA 2 Installing the CPU Backplate...
Page 40: ...English 33 Z490 AQUA 1 2 3...
Page 41: ...English 34 2 5 Installing the Motherboard 1 2 B A...
