500-003111-000
3-4
3.3.2
Bus Interrupter
To eliminate the processing overhead usually associated with ADC
polling, the VMIVME-3111 provides access to the VME interrupt structure through
the Bus Interrupter Module (BIM) shown in Figure 3.3.2-1. Control Registers for the
interrupter are located at relative addresses 10 and 18 (HEX) in the VMIVME-3111
assigned address space. These control registers are for INT0. Once the BIM has
been programmed and an A/D conversion has been started, the bus signals IACK,
IACKIN, and IRQ1 to IRQ7 control communication of the final NEW DATA RDY
flag to the VME controller. Details of interrupt control requirements are described in
Section 4.
3.4
ADC CONTROL AND TIMING
Control commands and status flags associated with controlling the ADC
are illustrated in Figure 3.4-1, and are described both in the following sections and
in Section 4.
3.4.1
Converter Controls and Status Flags
A conversion sequence is initiated by writing a "1" to the START
SETTLING and EN START CONV controls bits, and is composed of the following
consecutive time intervals:
a.
Settling
Delay
b.
Tracking
Interval
c.
Analog-to-Digital
Conversion
All ADC timing intervals discussed in this section are performed
automatically by the on-board smart controller. Program control of the converter
consists of basic handshake sequences.
The settling delay occurs directly after a state change has occurred in the
analog networks (such as selecting a new input channel), and represents the
settling time of the networks. After the settling delay has been completed, the
track-and-hold (T&H) amplifier (see Figure 1.2-1) enters the tracking mode and the
tracking interval begins.
During the tracking interval, the output of the T&H amplifier settles to a
value which is equal to its input voltage. The SETTLING BUSY flag is set HIGH at
the beginning of the settling delay, and is cleared LOW at the end of the tracking
interval. The CONV BUSY flag is set HIGH by the EN START CONV control bit,
and remains HIGH until the conversion sequence has been completed.
At the end of the tracking interval, the T&H amplifier enters the HOLD
MODE, in which the output of the amplifier is held at a constant level, and a CONV
CMD from the timing decoder causes the A/D conversion to begin. The A/D
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