Introduction
8
Measurement data is given a time stamp. The RISC processor is controlled by
interrupts and can also be addressed from the VME bus.
Data is exchanged via the memory connected to the DAMC. The connected
memory (SDRAM) is also managed by the DAMC. The VME bus and the Pow-
erPC can access this memory simultaneously.
Serial ETK Interface
The serial ETK interface is dc decoupled from the board. Three different modes
guarantee high performance to ensure that the ever increasing data volume
can be dealt with in the future:
•
the 8-MBit ’single mode’ guarantees compatibility to all previous ETKs,
•
the much faster 8-MBit ’block mode’ offers increased performance which
is particularly useful with bypass applications in ASCET-SD and when high
demands are made of the amount of data during data acquisition in INCA.
ES1231_1-ug-en.book Seite 8 Montag, 12. Mai 2003 12:37 12
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
