Artesyn Embedded Technology ATCA-7540, Installation And Use Manual, Page: 126 / 324

Maps and Registers
126 ATCA-7540 Installation and Use (6806871A01A )
5.1.5.2 IPMC I²C Register Map
Some FPGA registers may be accessed via IPMC Private I²C transactions (Slave address 0x7F).
See
Table 5-38 FPGA Register Map Overview. An IPMC write access to an address not listed in
this table or marked with a “-” in the IPMC I²C column is ignored. A corresponding read access
delivers always zero. The address offsets not mentioned below are not used and reserved for
future extensions. A reserved register is read-only and always deliver zero. A reserved bit is
read-only and always reads zero.
Table 5-38. FPGA Register Map Overview
LPC Address
Offset
LPC I/O IPMC I²C Description
0x00-0x01 r r Module Identification Register (See
Table 5-39
)
0x02 r r FPGA Version Register (See
Table 5-40
)
0x03 r/w r Serial Redirection Control Register (See
Table 5-41
)
0x04 r r/w Serial over LAN Control Register (See
Table 5-42
)
0x05 r r/w Serial Line Routing Register (See
Table 5-43
)
0x06 r r/w IPMC Power Level Register
0x07 r r/w IPMC Power Level Multiplier Register
0x08 - r ME Power Failure State Register (See
Table 5-44
)
0x09 - r ME Power Failure Cause Register (See,
Table 5-46
)
0x0A - r Payload Power Failure State Register (See
Table 5-47
)
0x0B - r Payload Power Failure Cause Register 1 (See
Table 5-49
)
0x0C - r Payload Power Failure Cause Register 2 (See
Table 5-50
)
0x0D - r Payload Power Failure Cause Register 3 (See
Table 5-51
)
0x0E - r Power Status Register (See
Table 5-52
)
0x10 r/w1c r BIOS Reset Source Register (See
Table 5-53
)
0x11 r/w r Reset Mask Register (See
Table 5-54
)
0x12 r/w1c r BIOS IPMC Watchdog Timeout Register (See
Table 5-55
)
0x13 w - BIOS Push Button Enable Register (See
Table 5-56
)
0x14 r/w1c r OS Reset Source Register (See
Table 5-57
)
0x15 r/w1c r OS IPMC Watchdog Timeout Register (See
Table 5-58
)