3-2
3.1.3.
The -HIZ Signal
The -HIZ signal is actively driven by the LSI2032 (U9). This Signal is available for monitor on
connector LA3. However, this signal should not be driven by the user.
3.1.4.
The Clock Circuitry
The SBC5307 uses a 45MHZ oscillator (U22) to provide the clock to CLK pin of the processor. In
addition to U22, there also exist a 20MHz oscillator which feeds into the Ethernet chip. The bus clock out
of the MCF5307 drives a clock buffer chip which is fed into the edge select pin of the MCF5307, the
ispLSI2032 for Ethernet timing (1/4 bus clock), SRAM (U19), and SDRAM (U23).
3.1.5.
Watchdog Timer (BUS MONITOR)
A bus cycle is initiated by the processor providing the necessary information for the bus cycle (e.g. address,
data, control signals, etc.) and asserting the -CS or -RAS low. Then, the processor waits for an
acknowledgment (-TA signal) from the addressed device before it can complete the bus cycle. It is possible
(due to incorrect programming) that the processor attempts to access part of the address space which
physically does not exist. In this case, the bus cycle will go on for ever, since there is no memory or I/O
device to provide an acknowledgment signal, and the processor will be in an infinite wait state. The
MCF5307 has the necessary logic built into the chip to watch the duration of the bus cycle. If the cycle is
not terminated within the preprogrammed duration the logic will internally assert a Transfer Error signal.
In response, the processor will terminate the bus cycle and an access fault exception (trap) will take place.
The duration of the Watchdog is selected by BMT0-1 bits in System Protection Register. The dBUG
initializes this register with the value 00, which provides for 1024 system clock time-out.
3.1.6.
Interrupt Sources
The ColdFire® family of processors can receive interrupts for seven levels of interrupt priorities. When the
processor receives an interrupt which has higher priority than the current interrupt mask (in status register),
it will perform an interrupt acknowledge cycle at the end of the current instruction cycle. This interrupt
acknowledge cycle indicates to the source of the interrupt that the request is being acknowledged and the
device should provide the proper vector number to indicate where the service routine for this interrupt level
is located. If the source of interrupt is not capable of providing a vector, its interrupt should be set up as
autovector interrupt which directs the processor to a predefined entry into the exception table (refer to the
MCF5307 User's Manual).
The processor goes to a service routine via the exception table. This table is in the Flash and the VBR
points to it. However, a copy of this table is made in the RAM starting at $00000000. To set an exception
vector, the user places the address of the exception handler in the appropriate vector in the vector table
located at $00000000, and then points the VBR to $00000000.
The MCF5307 has four external interrupt request lines. You can program the external interrupt request
pins to level 1, 3, 5, and 7 or levels 2, 4, 6, and 7. The SBC5307 configures these lines as level 1, 3, 5, and
7. There are also six internal interrupt requests from Timer1, Timer2, Software watchdog timer, UART1,
UART2, and MBUS. Each interrupt source, external and internal, can be programmed for any priority
level. In case of similar priority level, a second relative priority between 0 to 3 will be assigned.
