Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Signal Descriptions
Related information
on page 21
A.5 GFB manager interface signals
The
Generic Flash Bus
(GFB) manager interface connects to the process-specific part, and provides
the memory interface to the eFlash.
The following table shows the GFB signals.
Table A-6: GFB manager interface signals
Signal name
Direction Description
faddr[21:0]
Output
Address bus width is fixed at 22 bits, which allows access to a 4MB embedded Flash.
The
faddr[1:0]
bits are not used because the minimum data width is 32 bits.
fcmd[2:0]
Output
Command bus:
0b000
= IDLE.
0b001
= READ.
0b010
= WRITE.
0b011
= ROW WRITE.
0b100
= ERASE.
0b101
= Reserved.
0b110
= Reserved.
0b111
= MASS ERASE.
fabort
Output
Abort indication.
When HIGH, the manager requests to abort the command that is running.
fwdata[FWDATA_WIDTH−1:0]
Output
Write data bus.
frdata[FRDATA_WIDTH−1:0]
Input
Read data bus.
fready
Input
Command ready indication.
Driven LOW if the process-specific part requires wait states to complete the access.
Driven HIGH when the process-specific part is ready with the previous access and is
able to accept a new command.
fresp
Input
Flash error indication for the previously accepted command.
Driven HIGH for two cycles when an error is indicated for the command that is running.
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