Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Programmers Model
Interrupt method
Software enables the CMD_SUCCESS_IRQ and CMD_FAIL_IRQ interrupts, and waits for
either interrupt to be triggered. An interrupt occurs when a command enters the SUCCESS
or FAIL state.
To initiate a new transfer, software must write to the ADDR, DATA0, and CTRL registers. The CTRL
register must be written last because it triggers access to the embedded Flash. The command then
enters the queue until it is executed.
The CTRL, ADDR, and DATA0 register cannot be written in the following cases:
• CTRL register is not equal to 0.
• IRQ_STATUS register, bits[4:0], contain a pending interrupt bit.
IRQ_STATUS is an internal register that is not present in the programmers model. However, you
can access the value of IRQ_STATUS by reading the IRQ_STATUS _SET or IRQ_STATUS_CLR
register.
If these conditions are not met, the GFC-200 ignores the write to the CTRL, ADDR, or DATA0
registers and sets CMD_REJECT_IRQ = 1, to indicate a programming fault. This behavior ensures
that software does not change the value of a pending command on the GFB interface, and forces
software to process the result of the previously executed transaction.
Related information
Interrupt masked status register, IRQ_MASKED_STATUS
4.6 Preloading transfers
To improve the efficiency of ROW WRITE commands that use the command queue, transfers can
be preloaded to the CTRL register by enabling the CMD_ACCEPT_IRQ interrupt.
When the APB requester wants to achieve the efficiency benefits of a ROW WRITE command, it
must send the command for Flash transfers back-to-back, and keep the Flash in the high-voltage
programming state.
The following figure shows the ROW WRITE timing diagram.
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