Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Functional Description
Related information
AHB-Lite subordinate interface signals
on page 82
Partition configuration interface
on page 25
3.2.2 Primary APB completer interface
The primary APB completer interface enables read, write, and erase access to the embedded Flash,
if that partition has the appropriate R/W permissions set. It also acts as a control port for GFC-200
and the Flash macro.
The primary APB interface also provides direct access to a register interface that is external to
GFC-200. If the process-specific part contains programmable registers, then software can use the
primary APB interface to initialize its parameters such as the Flash interface access times.
The secondary APB interface does not have access to the external registers.
Address width
The address width is fixed at 13 bits, to allow for 2 × 4KB address spaces. One 4KB region is
for internal registers, and the other 4KB region is for external registers that might reside in the
process-specific part. The MSB,
paddr_s[12]
, selects either internal or external accesses.
See
on page 38 for a description of the APB completer interface
memory map.
Strobe signals
The strobe signals are checked for writes to ensure that all bits are set to 1 to indicate 32-bit word
accesses. Otherwise the write is ignored and has no effect on the registers. The strobe signals are
forwarded to the downstream APB requester, because the process-specific part might support byte
accesses.
Delayed response
Accesses to the internal register bank are serviced without delay. The design of the process-
specific register bank determines how much delay can be expected for accesses that target its
interface.
Error response
APB accesses to the internal register bank always give an OKAY response. For reads of reserved
addresses, the GFC-200 sets
prdata_s0
LOW. The GFC-200 ignores writes to a reserved address.
The response behavior to external register accesses depends on the implementation of the
attached process-specific register bank. Therefore, any errors that the APB requester interface
receives, are forwarded through the APB completer interface to the access initiator.
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