Arm
®
CoreLink™ GFC-200 Generic Flash Controller
Technical Reference Manual
Document ID: 101484_0000_01_en
Issue: 01
Signal Descriptions
Appendix A Signal Descriptions
Read this for a description of the input and output signals.
A.1 System interface signals
The system interface contains clock, reset, and interrupt signals. The interface also provides some
Flash power control and isolation signals.
The following table shows the system interface signals.
Table A-1: System interface signals
Signal name
Direction Description
clk
Input
Clock for all GFC-200 interfaces.
resetn
Input
Reset for GFC-200. Active-LOW.
You can set this signal LOW asynchronously, but set it HIGH synchronously with
clk
.
irq0
Output
Interrupt request to the primary domain. Active-HIGH.
irq1
Output
Interrupt request to the secondary domain. Active-HIGH.
flash_pwr_rdy
Output
Indicates that power to the Flash macro is stable. Active-HIGH.
The GFB receiver logic must monitor this signal and only initiate transactions towards the Flash macro
when
flash_pwr_rdy
is HIGH.
flash_pwr_opmode
Output
Indicates the Flash power operating mode to the GFB receiver logic:
0 = The Flash is in OPMODE_0 operational mode (default).
1 - The Flash is in OPMODE_1 operational mode.
flash_devisolaten
Output
Active-LOW isolation control output.
This signal controls isolation cells that isolate the Flash macro in the OFF and FULL_RET states.
flash_macro_resetn
Output
Active-LOW reset for Flash macros that require a powerup reset.
This reset is not intended for the process-specific part.
Related information
A.2 AHB-Lite subordinate interface signals
The AHB-Lite subordinate interface is a read-only port for accessing the Flash contents. The
interface includes the
hpart
sideband signal, that indicates whether the transfer originates from the
primary or secondary domain. The transfers that the GFC-200 receives are forwarded to the GFB
interface.
The following table shows the AHB-Lite subordinate interface signals.
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