Circuit Descriptions
© Copyright ARM Limited 1999. All rights reserved.
4-3
4.1.2
Clock generation
A PLL chip (U1) generates the high-speed clock, FCLK, which is used to clock the core
of ARM710T. The PLL chip has two programmable outputs, CLK and 2X which is
double the frequency of CLK.
The links, LK4 and LK5, can be used to set the frequency of the core clock, FCLK, as
shown in Table 2-1 on page 2-3.
The four links, GND, CLK, 2X, and EX, of LK5 allow the selection of clock source.
Only one link of LK5 should be fitted at any one time.
4.1.3
External clock input
A 50-ohm mini-coaxial connector socket is fitted on the board to allow a clock input to
be supplied from an external clock generator. The header card clock input is terminated
in a 47-ohm resistor, R25, on the board. The EX link of LK5 should be fitted before
applying an external clock source. R25 can be changed, if required, to allow proper
termination of a clock frequency source of other than 50-ohms output impedance.
