28
4.3
Clock System
CW6632B Bluetooth 3.0 Audio Player SOC
Version 1.0.0
Copyright ©2015, www.appotech.com. All Rights Reserved.
4.2.4
Port Wakeup Reset
During SLEEP mode, port wakeup event will cause CW6632B reset.
4.3
Clock System
4.3.1
Clock Control
CW6632B embeds 32K/4M/12M/24M OSC internal oscillator circuits. External crystal is needed to generate a clock
source. One internal PLL can generate 48MHz from the crystal clock source. One internal RC oscillator is also
embedded.
To make sure the USB module operate properly, the USB clock must set to be 48MHz. In this case, system clock
can be 48 MHz or 24MHz.
Register 4-2 PCON0
– Power control 0
Position
7
6
5
4
3
2
1
0
Name
DRAMCEN IRAMCEN IROMCEN
RAM2CEN IRCEN
IDLE
HOLD
SLEEP
Default
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DRAMCEN
: DECRAM clock enable
0 = Enable
1 = Disable
IRAMCEN
: IRAM clock enable
0 = Enable
1 = Disable
IROMCEN
: IROM clock enable
0 = Enable
1 = Disable
RAM2CEN
: RAM2 clock enable
0 = Enable
1 = Disable
IRCEN
: IR clock enable
0 = Enable
1 = Disable
IDLE
: IDLE mode
0 = Disable
1 = Enable IDLE mode
HOLD
: HOLD mode
0 = Disable
1 = Enable HOLD mode
SLEEP
: SLEEP mode
