APPOTECH CW6632B User Manual Download Page 26

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3.7

CPU and Memory related SFR Description

CW6632B Bluetooth 3.0 Audio Player SOC

Version 1.0.0

00 = IROM11 map to address 0xc000~0xffff

01 = IROM12 map to address 0xc000~0xffff

10 = IROM13 map to address 0xc000~0xffff

11 = IROM31 map to address 0xc000~0xffff

– Interrupt Enable 0

Position

Name

IE06

IE05

IE04

IE03

IE02

IE01

IE00

Default

Access

R/W

: Global interrupt enable

0 = Disable

1 = Enable

IE06

: USB SOF interrupt enable

0 = Disable

1 = Enable

IE05

: Huffman/UART1 overflow interrupt enable

0 = Disable

1 = Enable

IE04

: MP3 decoder and encoder interrupt enable

0 = Disable

1 = Enable

IE03

: Timer2 interrupt enable

0 = Disable

1 = Enable

IE02

: Timer1 interrupt enable

0 = Disable

1 = Enable

IE01

: SINT1/AGC interrupt enable

0 = Disable

1 = Enable

IE00

: SINT0 interrupt enable

0 = Disable

1 = Enable

– Interrupt Enable 1

Position

Name

IE17

IE16

IE15

IE14

IE13

IE12

IE11

IE10

Default

Access

R/W

Summary of Contents for CW6632B

Page 1: ...CW6632B Bluetooth 3 0 Audio Player SOC User Manual CW6632B UM EN Versions 1 0 0 Release Date 2015 8 25...

Page 2: ...3 2 1 3 Pin Description 3 3 CPU Core Information 6 3 1 Architecture 6 3 2 Instruction Set 6 3 3 Memory Mapping 9 3 3 1 Program Memory Mapping 9 3 3 2 External Data Memory Mapping 10 3 3 3 Internal Dat...

Page 3: ...r Saving Mode 39 5 1 1 BSleep Mode 39 5 1 2 Hold Mode 39 5 1 3 Idle Mode 39 5 1 4 Power Down Mode 40 5 2 Power Supply 40 6 General Purpose Input Output GPIO 44 6 1 Overview 44 6 2 Features 44 6 3 Func...

Page 4: ...og SFR 70 8 Universal Asynchronous Receiver Transmitter UART 71 8 1 UART0 71 8 1 1 Overview 71 8 1 2 UART0 Special Function Registers 71 8 2 UART1 73 8 2 1 Overview 73 8 2 2 UART1 Special Function Reg...

Page 5: ...2 207Bdata Operation 98 13 Audio Terminal DAC 99 13 1 Features 99 13 2 DAC Special Function Registers 99 13 2 1 DAC Register Mapping 99 13 2 2 Function of DAC Control Registers 100 13 3 Operation Gui...

Page 6: ...egister 111 16 3 Operation Guide 118 16 3 1 CPU RD WR 118 16 3 2 loop 118 16 3 3 DMA mode 119 17 PolyFuse control 120 17 1 PF Special Function Register 120 17 2 PF user guideline 121 18 Characteristic...

Page 7: ...1 6 HSP 1 2 A2DP 1 3 AVCTP 1 4 AVDTP 1 3 and AVRCP 1 5 Class 2 power level RF Performance Tx 0dBm Rx 80dBm Supports simple pairing and auto reconnection function High Performance 8051 at 48MHz Suppor...

Page 8: ...Synthesizer RF Rx Tx DAC Rx ADC RF Tx Bluetooth Baseband Core Peripherals IOs Watchdog SARADC Timer0 3 IIS EMI SDC SPI0 1 USB Host UART0 1 Port0 3 Clock Management Audio Acceleration Engine Power Man...

Page 9: ...3 4 5 6 7 8 9 P21 10 11 12 13 14 MICN MICP VCM AVSS VDDHP DACL DACR VCM_BUF P01 P00 P13 P32 P31 P30 P14 16 15 18 17 20 19 22 21 24 23 26 25 28 27 P07 PAD_VCC_IF VCC_RF VCC_PA RXTX GND_ANT1 VCC_VCO PAD...

Page 10: ...VCM output 4 AVSS GND Analog GND 5 VDDHP PWR Headphone power 6 DACL A DAC left output GPIO input 7 DACR A DAC right output GPIO input 8 P01 VCM_BUF I O GPIO AUXR0 UARTTX1 PORT INT WKUP0 SDDAT2 DAC VCM...

Page 11: ...wer VCC 17 RXTX A RF Rx and Tx pin 18 GND_ANT1 GND RF GND 19 VCC_VCO VCC_XO PAD_VDDQ PWR Power VCC VDDQ 20 XO_P A BT 26MHz XOSC Positive Pin 21 XO_N A BT 26MHz XOSC Negative Pin 22 BVIN PWR PMU Power...

Page 12: ...SRAM area 3 2 Instruction Set The instruction set of the AXC51 CORE is fully compatible with the standard MCS 51 TM instruction set standard 8051 development tools can be used to develop software for...

Page 13: ...code addr 1 or 3 2 ORL data addr A 1 3 ORL data addr data 1 2 ORL A data 1 2 ORL A data addr 1 1 ORL A Ri 1 1 ORL A Rn 1 2 JNC code addr 1 or 3 2 ANL data addr A 1 2 ANL data addr data 1 1 ANL A Ri 1...

Page 14: ...2 MOV C bit addr 1 1 INC DPTR 1 1 MUL AB 1 2 MOV Ri data addr 1 2 MOV Rn data addr 1 2 ANL C bit addr 1 2 CPL bit addr 1 2 CPL C 1 3 CJNE A data code addr 1 or 3 3 CJNE A data addr code addr 1 or 3 3...

Page 15: ...ds Clock Cycles running in IRAM 1 MOV A Rn 1 1 MOVX DPTR A 1 1 MOVX Ri A 1 1 CPL A 1 2 MOV data addr A 1 1 MOV Ri A 1 1 MOV Rn A 1 3 3 Memory Mapping 3 3 1 Program Memory Mapping As illustrated in CW6...

Page 16: ...x7FFF 0xFFFF 0x8000 0x9FFF 0xA000 SRAM1 Reserved 0x6400 256B Data RAM SRAM0 Reserved 0x1FFF 0x1F00 Figure 3 2 External Data Memory Mapping 3 3 3 Internal Data Memory Mapping Internal data memory locat...

Page 17: ...Reset value of SP Bit addressable space Figure 3 4 Lowest 32 bytes in Internal data memory Lower 128 3 4 Interrupt Processing 3 4 1 Interrupt sources The CW6632B provides 15 interrupt sources All inte...

Page 18: ...01B 0x401B 0x801B 3 4 TMR2CON 7 TMR2CON 6 IE0 3 IPH0 3 IP0 3 MP3 FFT1 0x0023 0x4023 0x8023 4 5 AUCON7 6 AUCON7 5 AUCON7 4 AUCON7 3 AUCON7 2 AUCON7 1 AUCON7 0 AUCON11 6 FFT1CON1 1 IE0 4 IPH0 4 IP0 4 Hu...

Page 19: ...which interrupt is allowed to take precedence The natural hierarchy is determined by analyzing potential interrupts in a sequential manner with the order listed in Table 3 2 The processor indicates t...

Page 20: ...ART1MINUS UART1LOOPCN T CLKCON2 ATCON10 ATCON9 FFT1CON1 FFT1CON 7898H ATCON8 ATCON7 DCT_CFG FIFO_BASE FIFO_SPEED AUCON11 KVADR KVCON2 7890H KVCON1 ATCON6 ATCON5 ATCON4 ATCON3 ATCON2 ATCON1 ATCON0 7888...

Page 21: ...PCON Data Pointer Configure Register Position 7 6 5 4 3 2 1 0 Name IA DPID0 DPID1 DPAID DPTSL EINSTEN DPSEL Default 1 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W IA Select Interrupt Vector s...

Page 22: ...6 5 4 3 2 1 0 Name DPH1 Default 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W The data pointers DPTR0 and DPTR1 are used to assign a memory address for the MOVX instructions This address can...

Page 23: ...gister 3 6 SP Stack Pointer Low Byte Position 7 6 5 4 3 2 1 0 Name SP Default 0 0 0 0 0 1 1 1 Access R W R W R W R W R W R W R W R W Register 3 7 SPH Stack Pointer High Byte Position 7 6 5 4 3 2 1 0 N...

Page 24: ...1 1 1 1 Access R W R W R W R W R W R W R W R W SINT0 Software 0 interrupts pending 0 No software 0 interrupt 1 Software 0 interrupt SINT1 Software 1 interrupts pending 0 No software 1 interrupt 1 Soft...

Page 25: ...30 P31 P32 INTADR_SEL interrupt address select 0 depend on DPCON IA 1 0x2000 PAPAMODE papa mode 0 normal mode 1 Parallel mode SPIINITMODE SPI Flash initial mode 0 normal mode 1 SPI initial mode SBCDEC...

Page 26: ...0 0 Access R W R W R W R W R W R W R W R W EA Global interrupt enable 0 Disable 1 Enable IE06 USB SOF interrupt enable 0 Disable 1 Enable IE05 Huffman UART1 overflow interrupt enable 0 Disable 1 Enab...

Page 27: ...Port interrupt enable 0 Disable 1 Enable IE11 SDC interrupt enable 0 Disable 1 Enable IE10 USB control interrupt enable 0 Disable 1 Enable Register 3 14 IPH0 Interrupt Priority high 0 Position 7 6 5 4...

Page 28: ...coder interrupts priority 11 level 3 highest priority 10 level 2 01 level 1 00 level 0 lowest priority IPH03 IP03 Timer2 interrupt priority 11 level 3 highest priority 10 level 2 01 level 1 00 level 0...

Page 29: ...riority 10 level 2 01 level 1 00 level 0 lowest priority IPH16 IP16 RTCC UART LVD WDT IIS interrupt priority 11 level 3 highest priority 10 level 2 01 level 1 00 level 0 lowest priority IPH15 IP15 Tim...

Page 30: ...Player SOC Version 1 0 0 Copyright 2015 www appotech com All Rights Reserved 11 level 3 highest priority 10 level 2 01 level 1 00 level 0 lowest priority IPH10 IP10 USB control interrupts priority 11...

Page 31: ...wer and ground User has to take into account this effect during board level design Figure 4 1 illustrates the power on and reset signals waveform during proper power on Internally there is TPOR and TR...

Page 32: ...e programming space and procedures to detect precise voltage level If user requires un precise voltage detection without fine voltage range LVD will be a good choice compared to ADC measurement XTable...

Page 33: ...t 30us for the internal band gap and comparator to become stable 5 Enable the LVD output by setting LVD_OEB 0 6 The EX_PIN detect voltage must be less than VDDIO Register 4 1 LVDCON LVD control Positi...

Page 34: ...is also embedded To make sure the USB module operate properly the USB clock must set to be 48MHz In this case system clock can be 48 MHz or 24MHz Register 4 2 PCON0 Power control 0 Position 7 6 5 4 3...

Page 35: ...Enable 1 Disable MP3CEN MP3 decoder clock enable 0 Enable 1 Disable IISCEN IIS clock enable 0 Enable 1 Disable TMRCEN Timer clock enable 0 Enable 1 Disable UARTCEN UART clock enable 0 Enable 1 Disabl...

Page 36: ...enable 0 Enable 1 Disable LVDCEN LVD clock enable 0 Enable 1 Disable ADCCEN ADC clock enable 0 Enable 1 Disable Register 4 5 PCON3 Power control 3 Position 7 6 5 4 3 2 1 0 Name XOSC32KEN XOSC12MEN BAS...

Page 37: ...1M 11 RC 4M or XOSC26M controlled by CLKCON2 3 WDTCSEL WDT clock section 0 Internal 32 KHz RC oscillator output 1 External 32 KHz or 12MHz crystal oscillator controlled by CLKCON2 6 and CLKCON2 7 as...

Page 38: ...tal oscillator 10 Select PLL 24MHz output invert 11 Select PLL 24MHz output xosc_ xosc_tclk pll_d2_ pll_d2 00 01 10 11 MUX eq_clk CLKCON1 7 6 PCON3 5 dac_clk PCON1 7 Figure 4 4 DAC clock select figure...

Page 39: ...l 12MHz crystal oscillator 01 Select PLL2 11 Select PLL2 div2 iis_clk xosc_tclk clk49m pll2_d2 00 01 10 11 MUX iis_bclk CLKCON2 5 4 iis_clk xosc_tclk clk49m pll2_d2 00 01 10 11 MUX iis_refclk CLKCON2...

Page 40: ...ock generators The PLL has reference clock from external 32 KHz 4M 12 M crystal oscillators to provide a stable reference clock and the reference clock is multiplied to provide the final PLL output Re...

Page 41: ...s 0 Disable 1 Enable PLL1DEN PLL digital module enables 0 Disable 1 Enable When change the divider also need write 1 to PLLDEN PLL1DEN32K PLL digital 32K enable 0 disable 1 enable X12EN XOSC 12M 374 d...

Page 42: ...25 set FOVER 1 and fraction fraction 1 2 integer integer 1 When the fraction is more than 0 80 set FOVER 1 and fraction fraction 2 integer integer FRAC fraction 65535 Register 4 15 PLL2CON PLL2 Config...

Page 43: ...0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W When the fraction is less than 0 25 set FOVER 1 and fraction fraction 1 2 integer integer 1 When the fraction is more than 0 80 set FOVER 1 and fract...

Page 45: ...system clock automatically 5 1 2 Hold Mode HOLD mode will stop the clock from entering to system The system clock is gated with the HOLD mode control Once enter HOLD mode clock to the system logic hal...

Page 46: ...e wake up 4 RTC every day wake up NOTE After exit Power Down mode by wakeup the device will be reset 5 2 Power Supply CW6632B provides two on chip low drop out regulators LDO to convert from 5V to 3 3...

Page 47: ...1 25V 101 vout 1 35V 110 vout 1 32V 111 vout 1 28V DZISEL2 0 ZERO_de current adjust 000 6 67uA 001 8 01uA 010 9 06uA 011 11 819uA 100 0 745uA 101 2 23uA 110 3 708uA 111 5 202uA Register 5 2 PWRCON2 P...

Page 48: ...0 disable LVD_EN LVD module enable 1 enable 0 disable LVD_OEB LVD output enable 1 enable 0 disable V33SEL1 V33SEL0 VDDIO voltage selection 00 2 8V 01 2 9V 10 3 0V 11 3 2V Register 5 4 PWRCON4 Power co...

Page 49: ...83 default 11 1 91 CURRENTSEL_D1 CURRENTSEL_D0 VDD core LDO amp bias current selection 00 X1 01 X2 10 X3 default 11 X4 Register 5 5 PWRCON5 Power control 5 Position 7 6 5 4 3 2 1 0 Name V18SELD1 V18SE...

Page 50: ...Enable internal pull up resistor using pull up resistor control register Select suitable pull up resistor value Enable internal pull up resistor using pull down resistor control register Select suitab...

Page 51: ...P11 C P12 C P13 ADC5 IISBCLK0 B P14 ADC2 SDDAT3 SPI0DOUT2 TMR3CAP TMR3PWM IISDO0 A P15 TMR3CKI B P16 BTUART1TX UARTTX0 Ir_input TMR2CAP TMR2PWM IISREF A P17 BTUART1RX TMR2CKI IISWS0 B P20 AUXL2 SDCMD...

Page 52: ...n Logic 1 indicates the occurrence of the selected trigger edge on the corresponding Port pins Upon reset logic 0 is set to all bits of WKPND Note 1 To Wakeup initialization to avoid any false signali...

Page 53: ...direction Register Position 7 6 5 4 3 2 1 0 Name P4DIR Default 1 1 1 1 1 1 Access R W R W R W R W R W R W P4xDIR P4x direction control 0 Output 1 Input Register 6 6 P0 P0 data register Position 7 6 5...

Page 54: ...w state when read and output low at P3x when write 1 P3x is in high state when read and output high at P3x when write Register 6 10 P4 P4 data register Position 7 6 5 4 3 2 1 0 Name P4 Default x x x x...

Page 55: ...wn Disable pull down 00h P2PD R W Enable pull down Disable pull down 00h P3PD R W Enable pull down Disable pull down 00h P4PD R W Enable pull down Disable pull down 00h Register 6 11 P1PUS0 P1 pull up...

Page 56: ...500 pull up 1x select 200K pull up P10PUS1 P10PUS0 00 select 10K pull up 01 select 500 pull up 1x select 200K pull up Register 6 13 P2PUS0 P2 pull up select Position 7 6 5 4 3 2 1 0 Name P27PUS0 P26P...

Page 57: ...P23PUS1 P23PUS0 00 select 10K pull up 01 select 500 pull up 1x select 200K pull up P22PUS1 P22PUS0 00 select 10K pull up 01 select 500 pull up 1x select 200K pull up P21PUS1 P21PUS0 00 select 10K pul...

Page 58: ...ull up 1x reverse P36PUS1 P36PUS0 00 select 10K pull up 01 reverse 1x reverse P35PUS1 P35PUS0 00 select 10K pull up 01 reverse 1x reverse P34PUS1 P34PUS0 00 select 10K pull up 01 select 500 pull up 1x...

Page 59: ...7PDS1 P16PDS1 P15PDS1 P14PDS1 P13PDS1 P12PDS1 P11PDS1 P10PDS1 Default 0 0 0 0 0 0 0 0 Access W R W R W R W R W R W R W R W R P17PDS1 P17PDS0 00 select 10K pull down 01 select 200 pull down 1x reverse...

Page 60: ...W R W R W R W R W R W R W R W R Register 6 20 P2PDS1 P2 pull down select Position 7 6 5 4 3 2 1 0 Name P27PDS1 P26PDS1 P25PDS1 P24PDS1 P23PDS1 P22PDS1 P21PDS1 P20PDS1 Default 0 0 0 0 0 0 0 0 Access W...

Page 61: ...lect 330 pull down Register 6 21 P3PDS0 P3 pull down select Position 7 6 5 4 3 2 1 0 Name P37PDS0 P36PDS0 P35PDS0 P34PDS0 P33PDS0 P32PDS0 P31PDS0 P30PDS0 Default 0 0 0 0 0 0 0 0 Access W R W R W R W R...

Page 62: ...1x select 330 pull down P30PDS1 P30PDS0 00 select 10K pull down 01 select 500 pull down 1x select 330 pull down Register 6 23 PIE0 Port digital input enable control Position 7 6 5 4 3 2 1 0 Name PIE0...

Page 63: ...1 1 1 1 1 1 Access RO R W R W R W R W R W R W R W PIE17 P37 Digital Input Enable Bit For VCMBUF 0 P37 digital Input Disabled 1 P37 digital Input Enabled PIE16 P35 Digital Input Enable Bit For UDSW 0 P...

Page 64: ...ble WKPIN_SEL Port interrupt wakeup event 2 sources selection 00 Select P34 01 Select DP 10 Select DM 11 Select IRTWKO SDTWO Dual SD card mode control 0 only support one SD card plugged in at the same...

Page 65: ...lt 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W PMUXCON2 PORT 2 Wake up enable 0 disable 1 enable Register 6 28 PMUXCON3 Port Function MUX control 3 Position 7 6 5 4 3 2 1 0 Name PMUXCON3 De...

Page 66: ...DM IRTWKO wakeup event occurred WKPND1 0 No INT1 wakeup event occurred 1 INT1 wakeup event occurred WKPND0 0 No INT0 wakeup event occurred 1 INT0 wakeup event occurred PWKEN3 0 Enable INT3 Wakeup 1 Di...

Page 67: ...e as outputs Reading from a data register reads the voltage levels of the corresponding port pins As illustrated in Figure 8 1 there are major differences reading the port values when the port is set...

Page 68: ...5 4 3 2 1 0 Name T0PND T0ES T0M T0IS T0PSR Default 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W T0PND Timer0 Pending Flag 0 Not Pending 1 Pending T0ES Timer0 Capture Mode Edge Select 0 CAP0...

Page 69: ...will be set 1 by hardware Register 7 3 TMR0PR Timer0 Period Position 7 6 5 4 3 2 1 0 Name TMR0PR Default 1 1 1 1 1 1 1 1 Access WO WO WO WO WO WO WO WO Note The overflow period of the timer is Tinc so...

Page 70: ...Counter Mode 10 Timer1 is enabled and works in PWM Mode 11 Timer1 is enabled and works in Capture Mode T1CPSEL Timer1 capture input pin select 0 Capture CAP1 1 Capture IR1 T1IS Timer1 Increase Source...

Page 71: ...lt 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Note Timer1 will increase in proper condition while it is enable it overflows when TMR1CNT TMR1PR TMR1CNT will be cleared to 0x0000 when overf...

Page 72: ...Capture Edge Select 00 CAP2 Rising Edge 01 CAP2 Falling Edge 1X CAP2 Rising Edge and Falling Edge T2M Timer2 Mode Select 00 Timer2 is disabled 01 Timer2 is enabled and works in Counter Mode 10 Timer2...

Page 73: ...g source events Register 7 12 TMR2CNTH TMR2CNTL Timer2 Counter Position 7 6 5 4 3 2 1 0 Name TMR2CNTH TMR2CNTL Default 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Note Timer2 will increase...

Page 74: ...ult 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W T3PND Timer3 Pending Flag 0 Not Pending 1 Pending T3ES Timer3 Capture Mode Edge Select 0 CAP3 Rising Edge 1 CAP3 Falling Edge T3M Timer3 Mode...

Page 75: ...ycle setting In capture mode the value of TMR3CNT will be captured to TMR3PWM when selected event occurs 7 5 Watchdog Timer WDT The Watchdog Timer WDT logic consists of a 20bit Watchdog Timer The Watc...

Page 76: ...1 0 Name WDTPD WDTTO CLRWDT WDTEN RSTEN WDTPS Default 0 0 0 1 1 1 0 1 Access RO RO WO R W R W R W R W R W WDTPD 0 read 0 before sleep operation 1 read 1 after sleep operation WDTTO 0 Read 0 after cle...

Page 77: ...ve pin RX UART0RX0 Transmit pin TX UART0TX0 When PSEL 1 Receive pin RX UART0RX1 Transmit pin TX UART0TX1 8 1 2 UART0 Special Function Registers Register 8 1 UARTCON UART0 control Position 7 6 5 4 3 2...

Page 78: ...ame UTRXNB FEF RXIF TXIF PSEL Default x x 0 1 0 Access R W R W R W RO R W UTRXNB The ninth bit data of receiver buffer FEF Frame Error Flag 0 the stop bit is 1 in the last received frame 1 the stop bi...

Page 79: ...6 5 4 3 2 1 0 Name UARTDATA Default x x x x x x x x Access R W R W R W R W R W R W R W R W Write this location will load the data to transmitter buffer And read this location will read the data from t...

Page 80: ...pt disable 1 Normal Receive interrupt enable or AUTO DMA mode Receive one word Interrupt enable OVERFLOWIE Receive DMA overflow interrupt enable 0 overflow Interrupt disable 1 overflow Interrupt enabl...

Page 81: ...UART1 divide register Position 7 6 5 4 3 2 1 0 Name UART1DIV Default 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W Register 8 10 UART1BAUD UART1 Baud Rate register Position 7 6 5 4 3 2 1 0 N...

Page 82: ...r you should write this register twice First write the higher byte then the low byte DMA address only map to SRAM1 Register 8 15 UART1MINUS UART1 DMA receive data minus byte count by CPU Portion 7 6 5...

Page 83: ...x x x X x x X x Access R O R O R O R O R O R O R O R O Register 8 20 UART1CNTL UART1 DMA receive count low byte Portion 7 6 5 4 3 2 1 0 Name UART1CNTL Defeault x x x x x x x x Access R O R O R O R O...

Page 84: ...ON Select DMA 4 Write the start DMA address For receive Write data to UARTDMARXPTR 5 Enable UART module by setting UTEN to 1 6 kick start a DMA receive process 7 Wait overflow or delay some time read...

Page 85: ...d XOSC26MEN Default 0 0 0 0 0 0 0 0 Access R W R W R W RO R W R W R W R W BTC2RS BTCON2 read select 0 read BTCONT register 1 read BT output state BTCDCLKO BT CDCLK output state BTCDCLKI BT CDCLK input...

Page 86: ...eceiver IR data then CPU can read IR data from IR data buffer 9 1 IR frame format Figure 9 1 shows the IR data frame format 9ms 45ms 32 bits data Figure 9 1 IR data frame format Figure 9 2 shows the I...

Page 87: ...EN IR enable 0 Disabled 1 Enabled Register 9 2 IRCON1 IR receiver control 1 register Position 7 6 5 4 3 2 1 0 Name IRCON1 Default 0 0 0 0 0 0 0 0 Access WO WO WO WO WO WO WO WO The IRCON1 is the entra...

Page 88: ...epeat pulse 2 3ms It is recommended to set REPEATCNT to 0x02 Fourth time for the ENDCONT Position 7 6 5 4 3 2 1 0 Name ENDCONT Default 1 0 0 0 0 0 0 0 When IR clock is 1 MHz ENDCONT 512 CLKCYC us is t...

Page 89: ...Default 0 0 0 0 0 0 0 0 Access RO RO RO RO RO RO RO RO Register 9 5 IRDAT2 IR receiver data buffer2 register Position 7 6 5 4 3 2 1 0 Name IRDAT2 Default 0 0 0 0 0 0 0 0 Access RO RO RO RO RO RO RO RO...

Page 90: ...as SPI0DI0 When PWKEDGE 6 0 and SPI0CON 3 1 Group1 actived 2wire mode P0 5 as SPI0CLK1 P0 4 as SPI0DIDO1 3wire mode P0 5 as SPI0CLK1 P0 4 as SPI0DO1 P0 6 as SPI0DI1 When PWKEDGE 6 1 and SPI0CON 3 0 Gr...

Page 91: ...A mode 0 TX 1 RX In 3 wire mode SPI0 can both Transmit and receive at the same time But when using DMA mode or 2 wire mode just one direction TX or RX is allowed Use this bit to select TX or RX SPI0WS...

Page 92: ...WO WO WO WO WO WO Nunit SPIDMACNT 1 Nbyte Nunit 2 SPIDMACNT 1 2 Register 10 5 SPIDMAPTRH SPI0 DMA Start Pointer high byte Position 7 6 5 4 3 2 1 0 Name SPIDMAPTRH Default x x x x x x x x Access WO WO...

Page 93: ...elect one of the four timing modes refer to XFigure 10 1X 6 Enable SPI0 module by setting SPI0EN to 1 7 Set SPI0IE 1 if needed 8 Write the start address to SPI0DMASP 9 Write data to SPI0DMACNT to kick...

Page 94: ...T SPI1 RX TX select bit in 2 wire or DMA mode 0 TX 1 RX In 3 wire mode SPI1 can both Transmit and receive at the same time But if we use DMA mode or 2 wire mode just one direction TX or RX is allowed...

Page 95: ...Pointer Position 7 6 5 4 3 2 1 0 Name SPI1DMASPL Default x x x x x x x x Access WO WO WO WO WO WO WO WO Register 10 12 SPI1DMACNTH SPI1 DMA Counter High byte Position 7 6 5 4 3 2 1 0 Name SPI1DMACNTH...

Page 96: ...PI1EN 1 6 Set SPI1IE 1 if needed 7 Write data to SPI1BUF to kick start the process 8 Wait for SPI1PND change to 1 or wait for interrupt 9 Read received data from SPI1BUF if needed 10 Go to Step 7 to s...

Page 97: ...1 EMI timing 11 1EMI Control Registers Register 11 1 EMICON0 EMI control0 Position 7 6 5 4 3 2 1 0 Name EMIEN EMIPW EMIHT EMIST Default 1 0 0 0 0 0 0 0 Access WO WO WO WO WO WO WO WO EMIEN When writin...

Page 98: ...cess RO R W R W R W R W R W R W R W EMIPND When Read EMI done flag 0 EMI is transmitting data 1 EMI is IDLE When Write 0 clear write buffer counter write 1 affect another CLKSEL PWM module work clock...

Page 99: ...or eight channels PWM of P2 When EMIM 0 emibuf0 will output to P2 Emibuf0 is updated with CPU write data When EMIM 1 and in no convert mode emibuf0 will output to P2 Emibuf0 is updated with SPI1 DMA d...

Page 100: ...MD SDCMD0 P20 SDCMD0 P3 1 SDDAT0 SDDAT00 P27 SDDAT00 P3 2 SDDAT1 SDDAT1 P0 0 SDDAT2 SDDAT2 P0 1 SDDAT3 SDDAT3 P1 4 12 3SDC Special Function Registers Register 12 1 SDCON0 SD host control register 0 Po...

Page 101: ...t 0 Disabled 1 Enabled Register 12 2 SDCON1 SD host control register 1 Position 7 6 5 4 3 2 1 0 Name CIE DIE CPND DPND CPCLR DPCLR 8CKE ORISE Default 0 0 0 0 0 0 0 0 Access R W R W RO RO WO WO R W R W...

Page 102: ...0 Inactive 1 Error detected DCRCE Data packet CRC error flag Update when the data CRC is receiving so it is only valid after operation read data is done 0 Enactive 1 Error detected NRPS No response re...

Page 103: ...mand Operation When command is kick started by writing one of the following kick start command to SDCFG 7 5 SD module sends out the pre set command After command has been sent it will kick start in on...

Page 104: ...data Operation Sending data 1 Configure DW4 SDCFG0 2 8CE SDCFG1 1 and ORISE SDCFG1 0 2 Write outgoing data to IRAM and set SDDPTR to point to starting address of data 3 Configure SDDCNT to the amount...

Page 105: ...gisters read write function Register 13 1 ATADR audio terminal address Position 7 6 5 4 3 2 1 0 Name DONE DIR ATADR Default x x x x x x x x Access RW RW RW RW RW RW RW RW DONE read write operation don...

Page 106: ...ata register low byte TRREGRH 11 DAC right channel trim data register high byte EQCON1 12 EQ configuration register1 EQCOF 13 EQ coefficient FIFO EQCON2 14 EQ configuration register2 EQVOLIN 15 EQ dat...

Page 107: ...0 Name SRSEL Default 0 0 0 1 Access RW RW RW RW SRSEL DAC FM sample rate select 0000 48 KHz 0001 44 1 KHz 0010 32 KHz 0011 Reserved 0100 24 KHz 0101 22 05 KHz 0110 16 KHz 0111 Reserved 1000 12 KHz 100...

Page 108: ...ame DACVSET DACVSTEP DACVEN DACVSTEP Default 0 0 0 0 0 Access WO R W R W R W R W DACVSET Direct set DAC volume value Write 1 to direct set DAC volume value Write 0 affects nothing DACVEN DAC volume ad...

Page 109: ...1 0 Name DIRETR DIRETL TRIMMTL TRIMMTR TMDONE TRIMKST Default 0 0 0 0 0 0 Access RW RW RW RW RW RW DIRETR DAC right trim direction 0 Trim data decrease one step one sample 1 Trim data add one step one...

Page 110: ...data high byte Register 13 13 TRREGRL DAC right channel trim data reg law byte Position 7 6 5 4 3 2 1 0 Name TRIMREGRL Default Access RW RW RW RW RW RW RW RW TRIMREGRL Write DAC anticipant trimming d...

Page 111: ...on clock must be slower than 1 MHz 14 2ADC Pin Mapping Table 14 1 pin used ADC Channel Function Description ADC10 TP3 ADC9 TP2 ADC8 P26 Only for PIN detected Not for ADKEY ADC7 LDO Band GAP Reference...

Page 112: ...CSEL ADC Channel Select 0000 P3 3 ADC0 0001 P2 1 ADC1 0010 P1 4 ADC2 0011 P2 2 ADC3 0100 P3 0 ADC4 0101 P1 3 ADC5 0110 1 2 Battery voltage 0111 LDO_BG 0 864V 1000 P26 ADC8 Only for PIN detected Not fo...

Page 113: ...efault x x x x x x Access WO WO WO WO WO WO ADC conversion clock system clock 2 x ADCBAUD 1 Register 14 4 ADCDATAL SARADC Buffer low byte control Position 7 6 5 4 3 2 1 0 Name ADCDATAL Default x x Acc...

Page 114: ...as CRC x X 16 X 12 X 5 1 Figure 15 1 shows CRC FIFO block diagram CRC FIFO High Byte CRC FIFO Low Byte CPU Read CRC FIFO CPU Write CRC FIFO CPU data BUS Figure 15 1 CRC FIFO block diagram Write CRCRE...

Page 115: ...CRCRES1 Default x x x x x x x x Access RO RO RO RO RO RO RO RO 15 2LFSR16 15 2 1 Features Software can control lfsr16 or enable CRCEN of SPI1CON1 1 hardware can auto trigger lfsr16 when spi1 receive...

Page 116: ...itial the LFSR32 register user need to write this register 4 times to LFSR32 register for LFSR32 High byte first Reading will output LFSR32 data0 Register 15 8 LFSR32_DAT1 LFSR32 data 1 Position 7 6 5...

Page 117: ...tion P_SEL 0 P_SEL 1 P_SEL 0 P_SEL 1 IISREFCLK P16 IIS Reference Clock IISWS P17 P26 P17 P26 IIS Word Select IISBCLK P13 P25 P13 P25 IIS Bit Clock IISDI P06 P23 P14 P22 IIS Data In IISDO P14 P22 P14 P...

Page 118: ...enable Register 16 2 IIS_CON1 Position 7 6 5 4 3 2 1 0 Name DMA_LOOP SMP_SYNC IIS_3W OP_MOD TXRX_MOD Default 0 0 0 1 0 0 0 0 Access R W R W R W R W R W R W R W R W DMA_LOOP IIS DMA data to memory the...

Page 119: ...PND error flag when ws be shorter suddenly will cause some error R 0 not error 1 error W 0 clear 1 not clear TX_BUF_EPT indicate tx buffer empty or not R 0 not empty then CPU can not write data to sen...

Page 120: ...guration Position 7 6 5 4 3 2 1 0 Name P_SEL IIS_OV_RD_IE IIS_OVF_WR_IE IIS_HF_RD_IE IIS_HF_WR_IE Default 0 0 0 0 0 Access R W R W R W R W R W P_Sel Choose the ports of do di ws and bclk 0 IISDO P14 I...

Page 121: ...k period when transmit or receive bit count less than this value BCLK period cal by iis_clk BAUDRATE 1 when bigger or equal this value BCLK become to iis_clk BAUDRATE 2 e g Fiis Fsample IIS_ALLBIT 1 2...

Page 122: ...WSCNT0 1 calcute bclks between a ws period Position 7 6 5 4 3 2 1 0 Name IIS_WSCNT0 1 Default x x x x x x x x Access R R W R R R R R R IIS_WSCNT0 1 calculate iis_bclk between a ws period Write only wr...

Page 123: ...ly write IIS_DMA_RD_CNT0 8 bits this register is the low bits secondly write IIS_DMA_RD_CNT1 2 bits this register is the high bits write this register is the same time to kick start DMA transfer For i...

Page 124: ...ration Guide 16 3 1 CPU RD WR For 2 wire data mode set IO direction 1 wire Data input output hardware auto control configure other IO direction Such as WS BCLK REFCLK if need if master mode set BAUDRA...

Page 125: ...2015 www appotech com All Rights Reserved 16 3 3 DMA mode 1 conf IIS_ADR0 and IIS_ADR1 2 conf IIS_BAUD IIS_BCLK_CFG IIS_VALBIT IIS_ALLBIT 3 conf IIS_CON0 1 4 conf IIS_DMA_RD_CNT and IIS_DMA_WR_CNT to...

Page 126: ...1 pf access done pf_avdden 0 pf avdd disable 1 pf avdd enable pf_rw 0 read pf operation 1 program pf operation pf_cs 0 pf cs disable 1 pf cs enable Register 17 2 PFBAUD Position 7 6 5 4 3 2 1 0 Name...

Page 127: ...for program timing clear wr_enc steps 1 set pf_rw for write operation delay for correct timing steps 2 set pf_avdden delay for correct timing steps 3 set pf_cs delay for correct timing steps 4 write...

Page 128: ...rs Sym Characteristics Min Typ Max Unit Conditions FI1 Frequency input 32 768 KHz Low frequency OSC FI2 Frequency input 1 12 15 MHz High frequency OSC FOUT1 Frequency output 48 MHz TLOCK1 PLL locked t...

Page 129: ...voltage 2 6 V 10Kohm loading ADC SNR DR 93 dB In Voice Band ADC THD N 89 dB In Voice Band 18 5USB PHY Parameters Table 18 5 USB PHY Parameters Sym Characteristics Min Typ Max Unit Conditions RDMPUP D...

Page 130: ...Mixer Conversion Gain 0 dB Ifamp Gain 5 9 12 15 18 dB 12 Complex BPF Band pass 3 dB BW Figure 1 2 MHz Image Rejection 30 dB VGA Gain Range 6 68 dB Gain Step 1 6 dB ADMOD SNDR Freq BW 50 dB Table 18 8...

Page 133: ...B Bluetooth 3 0 Audio Player SOC Version 1 0 0 Copyright 2015 www appotech com All Rights Reserved Revision History Date Version Comments Revised by 2015 8 28 0 0 1 Initial version YX 2015 8 28 0 0 2...

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