Evaluation Board User Guide
UG-XXX
Figure 16. Main Window
Noise Test—Quick Start Demonstration
To perform a noise test using the AD7124-8 evaluation board,
LK5 should be inserted so that AIN0 and AIN1 are connected
together.
1.
Click
ADC Setup
to open the
AD7124-8 Register Interface
window. The AD7124-8 should be configured as follows:
a.
In the ADC_Control register, select the full power
mode.
b.
Provide a bias voltage to the analog input by enabling
the VBIAS0 in the IO_Control_2 register.
c.
In the Channel 0 register, AIN0 is connected to the
positive input, AIN1 is connected to the negative
input of the ADC for this channel, and Setup 0 is
selected. Therefore, the AIN0 to AIN1 conversion is
mapped using the Setup 0 configuration.
d.
Setup 0 is configured with the following register settings:
i.
In the Config_0 register, the external reference is
selected as the reference source for the ADC
conversion.
ii.
In the Filter_0 register, FS0 is set to 2047 and the
sinc4 filter is selected. This sets the output data
rate to 9.38 sps.
iii.
In the Offset_0 register, the default offset register
value is selected.
iv.
In the Gain_0 register, the factory trimmed gain
error value is selected.
2.
Figure 17 shows the contents of the
AD7124-8 Register
Interface
and the state of the AD7124-8 registers. Click
OK
to return to the main window. Figure 18 shows an example
of the main window after running a noise test.
3.
Set the number of samples to be collected in each batch in
the
Samples
box, which is located just to the left of
Start
Sampling
, near the top right hand corner of the main
window.
4.
Click
Start Sampling
to acquire samples from the ADC.
Rev. PrA | Page 13 of 36
Summary of Contents for UG Series
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Page 20: ...UG XXX Evaluation Board User Guide Figure 23 Schematic Regulators Rev PrA Page 20 of 36 ...
Page 21: ...Evaluation Board User Guide UG XXX Figure 24 Schematic SDP Rev PrA Page 21 of 36 ...
Page 23: ...Evaluation Board User Guide UG XXX Figure 26 Layer 1 Component Side Rev PrA Page 23 of 36 ...
Page 24: ...UG XXX Evaluation Board User Guide Figure 27 Layer 2 Ground Plane Rev PrA Page 24 of 36 ...
Page 25: ...Evaluation Board User Guide UG XXX Figure 28 Layer 3 Power Ground Plane Rev PrA Page 25 of 36 ...
Page 26: ...UG XXX Evaluation Board User Guide Figure 29 Layer 4 Component Side Rev PrA Page 26 of 36 ...
