Analog Devices TigerSHARC ADSP-TS201S Specifications Download | Manualshive

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Rev. C

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Page 8 of 48

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December 2006

ADSP-TS201S

external memory. These transfers only use handshake
mode protocol. DMA priority rotates between the four
receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA

channels transfer data received from an external bus master
to internal memory or to link port I/O. These transfers only
use slave mode protocol, and an external bus master must
initiate the transfer.

The DMA controller provides these additional features:

• Flyby transfers. Flyby operations only occur through the

external port (DMA Channel 0) and do not involve the
DSP’s core. The DMA controller acts as a conduit to trans-
fer data from an I/O device to external SDRAM memory.

During a transaction, the DSP relinquishes the external
data bus; outputs addresses and memory selects
(MSSD3–0); outputs the IORD, IOWR, IOEN, and
RD/WR strobes; and responds to ACK.

• DMA chaining. DMA chaining operations enable applica-

tions to automatically link one DMA transfer sequence to
another for continuous transmission. The sequences can
occur over different DMA channels and have different
transmission attributes.

• Two-dimensional transfers. The DMA controller can

access and transfer two-dimensional memory arrays on any
DMA transmit or receive channel. These transfers are
implemented with index, count, and modify registers for
both the X and Y dimensions.

Figure 4. ADSP-TS201S Shared Memory Multiprocessing System

CLKS/REFS

ADDR31–0

DATA31–0

BR1

BR7–2,0

ADDR31–0

DATA31–0

BR0

BR7–1

BMS

CONTROL

ADSP-TS201S #0

CONTROL

ADSP-TS201S #1

ADSP-TS201S #7
ADSP-TS201S #6
ADSP-TS201S #5
ADSP-TS201S #4
ADSP-TS201S #3
ADSP-TS201S #2

RESET

RST_IN

ID2–0

CLKS/REFS

SCLK_V

REF

V

REF

SCLK

SCLKRAT2–0

000

CLOCK

REFERENCE

ADDR

DATA

HOST

PROCESSOR

INTERFACE
(OPTIONAL)

ACK

GLOBAL

MEMORY

AND

PERIPHERALS

(OPTIONAL)

OE

ADDR

DATA

CS

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

RD

MS1–0

ACK

ID2–0

001

HBG

HBR

BOFF

BRST

CS

WE

WRL

C

O

N

T

R

O

L

A

D

D

R

E

S

S

D

A

T

A

C

O

N

T

R

O

L

A

D

D

R

E

S

S

D

A

T

A

SDRAM MEMORY

(OPTIONAL)

MSSD3–0

IORD

IOEN

RAS

CAS

LDQM

SDWE

SDCKE

SDA10

CS
RAS
CAS

DQM

WE

CKE

A10

ADDR

DATA

CLK

MSH

DMAR3–0

DPA

CPA

LINK

DEVICES

(2 MAX)

(OPTIONAL)

LxCLKINP/N

LxACKO

LxDATI3–0P/N

LxBCMPI

LxBCMPO

LxDATO3–0P/N

LxCLKOUTP/N

LxACKI

TMR0E

BM

CONTROLIMP1–0

LINK

IRQ3–0

FLAG3–0

LINK

RST_IN

BUSLOCK

CLOCK

DS2–0

IOWR

JTAG

POR_IN

RST_OUT

REFERENCE

LINK

DEVICES

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Summary of Contents for TigerSHARC ADSP-TS201S

Page 1: ...hip emulation Single precision IEEE 32 bit and extended precision 40 bit floating point data formats and 8 16 32 and 64 bit fixed point data formats KEY BENEFITS Provides high performance static super...

Page 2: ...11 Pin Function Descriptions 12 Strap Pin Function Descriptions 20 ADSP TS201S Specifications 21 Operating Conditions 21 Electrical Characteristics 22 Package Information 23 Absolute Maximum Ratings...

Page 3: ...rupt controller that supports hardware and soft ware interrupts supports level or edge triggers and supports prioritized nested interrupts Four 128 bit internal data buses each connecting to the six 4...

Page 4: ...ns four computational units an ALU a multiplier a 64 bit shifter a 128 bit CLU and a 32 word register file Register File each compute block has a multiported 32 word fully orthogonal register file use...

Page 5: ...either level sensitive or edge sensitive except the IRQ3 0 hardware interrupts which are programmable The DSP distinguishes between hardware interrupts and soft ware exceptions handling them differen...

Page 6: ...er 32 bits of the external data bus connect to even addresses and the upper 32 bits connect to odd addresses The external port supports pipelined slow and SDRAM proto cols Addressing of external memor...

Page 7: ...fairness feature prevents one DSP from holding the external bus too long The DSP s four link ports provide a second path for interproces sor communications with throughput of 4G bytes per second The...

Page 8: ...r different DMA channels and have different transmission attributes Two dimensional transfers The DMA controller can access and transfer two dimensional memory arrays on any DMA transmit or receive ch...

Page 9: ...y can provide the test for conditional branching RESET AND BOOTING The ADSP TS201S processor has three levels of reset Power up reset after power up of the system SCLK all static inputs and strap pins...

Page 10: ...asing productivity Statistical profiling enables the programmer to nonintrusively poll the processor as it is running the program This feature unique to VisualDSP enables the software developer to pas...

Page 11: ...use as a cost effective method to learn more about developing or prototyping applications with Analog Devices processors platforms and software tools Each EZ KIT Lite includes an evaluation board alon...

Page 12: ...e SCLK I na System Clock Input The DSP s system input clock for cluster bus The core clock rate is user programmable using the SCLKRATx pins For more information see Clock Domains on Page 9 RST_IN I A...

Page 13: ...lave devices can deassert ACK to add wait states to external memory accesses ACK is used by I O devices memory controllers and other periph eralsonthedataphase TheDSPcandeassertACKtoaddwaitstatestorea...

Page 14: ...SDCKE LDQM and HDQM pins and the DSP puts the SDRAM in self refresh mode The DSP asserts HBG until the host deasserts HBR In multiprocessor systems the current bus master DSP drives HBG and all slave...

Page 15: ...e IOEN makes the I O device drive the data instead of the TigerSHARC IOEN O T pu_0 nc I O Device Output Enable Enables the output buffers of an external I O device for fly by transactions between the...

Page 16: ...ive when accessing an even address in word accesses or when memory is configured for a 32 bit bus to disable the write of the high word SDA10 O T pu_0 nc SDRAM Address Bit 10 Separate A10 signals enab...

Page 17: ...onnect directly to VDD_IO VSS connect directly to VSS 1 See the reference on Page 11 to the JTAG emulation technical reference EE 68 Table 10 Pin Definitions Flags Interrupts and Timer Signal Type Ter...

Page 18: ...ermination of unused pins column symbols epd external pull down approximately 5 k to VSS epu external pull up approx imately 5 k to VDD_IO nc not connected na not applicable always used VDD_IO connect...

Page 19: ...RST VREF can be connected to a power supply or set by a voltage divider circuit as shown in Figure 6 For more information see Filtering Reference Voltage and Clocks on Page 10 SCLK_VREF I na System Cl...

Page 20: ...h Table 17 shows the resistors that are enabled during active reset and during normal operation Table 16 Pin Definitions I O Strap Pins Signal Type at Reset On Pin Description EBOOT I pd_0 BMS EPROM B...

Page 21: ...K FLAG3 0 DS2 0 ENEDREG 3 Values represent dc case During transitions the inputs may overshoot or undershoot to the voltage shown in Table 18 based on the transient duty cycle The dc case is equivalen...

Page 22: ...put Voltage1 VDD_IO Min IOL 4 mA 0 4 V IIH High Level Input Current VDD_IO Max VIN VIH Max 20 A IIH_PU High Level Input Current VDD_IO Max VIN VIH Max 20 A IIH_PD High Level Input Current VDD_IO Max V...

Page 23: ...Type Z Lead Free Option optional ccc See Ordering Guide LLLLLLLLL L Silicon Lot Number R R Silicon Revision yyww Date Code vvvvvv Assembly Lot Code LLLLLLLLL L 2 0 tppZ ccc T ADSP TS20xS a yyww count...

Page 24: ...tput drive strengths refer to Figure 37 on Page 38 through Figure 44 on Page 39 Rise and Fall Time vs Load Capacitance and Figure 45 on Page 39 Out put Valid vs Load Capacitance and Drive Strength The...

Page 25: ...age 12 2 For more information see Clock Domains on Page 9 3 The value of tSCLK SCLKRAT2 0 must not violate the specification for tCCLK 4 System clock transition times apply to minimum SCLK cycle time...

Page 26: ...Min Max Unit Timing Requirements tRST_IN_PWR RST_IN Deasserted After VDD VDD_A VDD_IO VDD_DRAM SCLK and Static Strap Pins Stable 2 ms tTRST_IN_PWR 1 TRST Asserted During Power Up Reset 100 tSCLK ns S...

Page 27: ...ing Characteristic tRST_OUT RST_OUT Deasserted After RST_IN Deasserted 1 5 ms Figure 14 Normal Reset Timing Table 28 On Chip DRAM Refresh1 Parameter Min Max Unit Timing Requirement tREF On chip DRAM R...

Page 28: ...Low Word SDRAM Data Mask 4 0 1 0 1 15 2 0 SCLK HDQM High Word SDRAM Data Mask 4 0 1 0 1 15 2 0 SCLK SDA10 SDRAM ADDR10 4 0 1 0 1 15 2 0 SCLK HBR Host Bus Request 1 5 0 5 SCLK HBG Host Bus Grant 1 5 0...

Page 29: ...tions applicable during reset only 11 JTAG system pins include RST_IN RST_OUT POR_IN IRQ3 0 DMAR3 0 HBR BOFF MS1 0 MSH SDCKE LDQM HDQM BMS IOWR IORD BM EMU SDA10 IOEN BUSLOCK TMR0E DATA63 0 ADDR31 0 R...

Page 30: ...utput Voltage Low VO_P or VO_N RL 100 0 92 V VOD Output Differential Voltage RL 100 300 650 mV IOS Short Circuit Output Current VO_P or VO_N 0 V 5 55 mA VOD 0 V 10 mA VOCM Common Mode Output Voltage 1...

Page 31: ...CR tCCLK 0 10 tCCLK 1 4 8 0 25 LCR tCCLK 0 15 tCCLK 1 5 6 8 0 25 LCR tCCLK 0 30 tCCLK 1 7 8 ns ns ns tLACKID Delay from LxACKI rising edge to first transmission clock edge Figure 21 16 LCR tCCLK 1 2 n...

Page 32: ...CLKOL tLCLKOH tLCLKOP VOD MIN VOD MIN VOD 0V tREO tFEO VO_N VO_P RL CL CL_P CL_N RL 100 CL 0 1pF CL_P 5pF CL_N 5pF Figure 20 Link Ports Data Output Setup and Hold1 1 These parameters are valid for bot...

Page 33: ...n End and Stops Figure 23 Link Ports Back to Back Transmission LxCLKOUT LxDATO VOD 0V VOD 0V FIRST EDGE OF 5TH SHORT WORD IN A QUAD WORD tLACKIS tBCMPOH LxACKI LxBCMPO tLACKIH LAST EDGE IN A QUAD WORD...

Page 34: ...s tLDIS LxDATI Input Setup Figure 25 0 201 2 0 251 3 0 301 4 0 351 5 ns ns ns ns tLDIH LxDATI Input Hold Figure 25 0 201 2 0 251 3 0 301 4 0 351 5 ns ns ns ns tBCMPIS LxBCMPI Setup Figure 24 2 tLCLKIP...

Page 35: ...SP TS201S Rev C Page 35 of 48 December 2006 Figure 25 Link Ports Data Input Setup and Hold1 1 These parameters are valid for both clock edges LxCLKIN LxDATI VOD 0V VOD 0V tLDIS tLDIH tLDIS tLDIH tLCLK...

Page 36: ..._IO 2 5V 25 C VDD_IO 2 63V 40 C OUTPUT PIN VOLTAGE V 0 2 8 0 4 0 8 1 2 1 6 2 0 2 4 OUTPUT PIN CURRENT mA 5 0 5 VDD_IO 2 38V 105 C 10 15 20 25 10 15 20 25 30 STRENGTH 1 VDD_IO 2 5V 25 C VDD_IO 2 63V 40...

Page 37: ...rents at Strength 6 Figure 33 Typical Drive Currents at Strength 7 OUTPUT PIN VOLTAGE V 0 2 8 0 4 0 8 1 2 1 6 2 0 2 4 OUTPUT PIN CURRENT mA 11 0 11 VDD_IO 2 38V 105 C 22 33 44 66 22 33 44 66 88 STRENG...

Page 38: ...does not apply to output disable delays see Output Disable Time on Page 37 The graphs of Figure 37 through Figure 45 may not be linear outside the ranges shown Figure 36 Equivalent Device Loading for...

Page 39: ...ANCE pF 0 10 20 30 40 50 60 70 80 90 100 0 5 10 15 20 25 RISE TIME Y 0 0377x 0 7449 FALL TIME Y 0 0374x 0 851 STRENGTH 6 VDD_IO 2 5V Figure 44 Typical Output Rise and Fall Time 10 to 90 VDD_IO 2 5 V v...

Page 40: ...ir flow source may be required Table 34 shows the thermal characteristics of the 25 mm 25 mm BGA_ED package All parameters are based on a JESD51 9 four layer 2s2p board All data are based on 3 W power...

Page 41: ...l assignments Figure 46 576 Ball BGA_ED Pin Configurations1 Top View Summary 1 For a more detailed pin summary diagram see the EE 179 ADSP TS201S System Design Guidelines on the Analog Devices website...

Page 42: ...ADDR26 D19 ADDR27 A20 ADDR28 B20 ADDR29 C20 ADDR24 D20 ADDR25 A21 ADDR22 B21 ADDR23 C21 ADDR20 D21 VSS A22 VSS B22 VSS C22 VSS D22 ADDR19 A23 ADDR21 B23 VSS C23 VDD_IO D23 ADDR17 A24 VSS B24 ADDR18 C...

Page 43: ..._P K24 L0CLKINP L24 L0DATI2_P M24 L0DATO3_P N1 ID0 P1 SCLK R1 VSS T1 RST_IN N2 VSS P2 SCLK_VREF R2 NC SCLK 1 T2 SCLKRAT2 N3 VDD_A P3 VSS R3 NC SCLK_VREF 1 T3 BR4 N4 VDD_A P4 BM R4 BR7 T4 DS0 N5 VDD_IO...

Page 44: ...DMAR2 AD6 DMAR3 AA7 DMAR0 AB7 DMAR1 AC7 CPA AD7 DPA AA8 HBR AB8 HBG AC8 BOFF AD8 BUSLOCK AA9 L3BCMPO AB9 L3ACKI AC9 L3DATO0_N AD9 L3DATO0_P AA10 L3DATO1_N AB10 L3DATO1_P AC10 L3CLKON AD10 L3CLKOP AA1...

Page 45: ...N MILLIMETERS 2 THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0 25 mm OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES 3 CENTER DIMENSIONS ARE NOMINAL 4 THIS PACKAGE CONFORMS TO JEDEC MS 034 SPECI...

Page 46: ...P 576 576 Ball BGA_ED ADSP TS201SABP 050 40 C to 85 C 500 MHz 24M bit 1 05 VDD 2 5 VDD_IO 1 5 VDD_DRAM BP 576 576 Ball BGA_ED ADSP TS201SYBP 050 40 C to 105 C 500 MHz 24M bit 1 05 VDD 2 5 VDD_IO 1 5 V...

Page 47: ...ADSP TS201S Rev C Page 47 of 48 December 2006...

Page 48: ...Rev C Page 48 of 48 December 2006 ADSP TS201S 2006 Analog Devices Inc All rights reserved Trademarks and registered trademarks are the property of their respective owners D04324 0 11 06 C...

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