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dc1416fa

DEMO MANUAL DC1416

LT 0218 REV A • PRINTED IN USA

 

ANALOG DEVICES, INC. 2016

ESD Caution 

ESD (electrostatic discharge) sensitive device.

 Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection 

circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality.

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By using the evaluation board discussed herein (together with any tools, components documentation or support materials, the “Evaluation Board”), you are agreeing to be bound by the terms and 

conditions set forth below (“Agreement”) unless you have purchased the Evaluation Board, in which case the Analog Devices Standard Terms and Conditions of Sale shall govern. Do not use the Evaluation 

Board until you have read and agreed to the Agreement. Your use of the Evaluation Board shall signify your acceptance of the Agreement. This Agreement is made by and between you (“Customer”) 

and Analog Devices, Inc. (“ADI”), with its principal place of business at One Technology Way, Norwood, MA 02062, USA. Subject to the terms and conditions of the Agreement, ADI hereby grants to 

Customer a free, limited, personal, temporary, non-exclusive, non-sublicensable, non-transferable license to use the Evaluation Board FOR EVALUATION PURPOSES ONLY. Customer understands and 

agrees that the Evaluation Board is provided for the sole and exclusive purpose referenced above, and agrees not to use the Evaluation Board for any other purpose. Furthermore, the license granted 

is expressly made subject to the following additional limitations: Customer shall not (i) rent, lease, display, sell, transfer, assign, sublicense, or distribute the Evaluation Board; and (ii) permit any Third 

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use of the Evaluation Board or termination of this Agreement, Customer agrees to promptly return the Evaluation Board to ADI. ADDITIONAL RESTRICTIONS. Customer may not disassemble, decompile 

or reverse engineer chips on the Evaluation Board. Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board, including but not limited 

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Summary of Contents for LT1222

Page 1: ...1793 BF8621 6 pA en Input Voltage Noise Density f 100kHz JFET In Gain Configuration 1 nV Hz en Input Voltage Noise Density f 100kHz Source Follower Configuration 3 nV Hz CIN Input Capacitance f 10kHz Source Follower Configuration 2 pF GBW Gain Bandwidth Product JP In CCOMP 49pF 70 MHz GBW Gain Bandwidth Product JP Out CCOMP 10pF 190 MHz GBW Gain Bandwidth Product JP Out C7 Removed CCOMP 0pF 500 MH...

Page 2: ...w the procedure below 1 With power off connect the 12V 12V and Com leads from the power supply to the V V and GND terminals of the demo circuit as shown in Figure 1 2 With power off connect the VOUT of the demo circuit to an oscilloscope or DMM You can use either the gold SMA connector or the turrets provided on board or both Set a high range such as 2V DIV on the oscil loscope or VDC on the DMM 3...

Page 3: ...1x3 JFET Drain 1 2 1 2 2 3 2 3 JP2 2x3 JFET Source 1 2 1 2 5 6 3 4 JP3 1x3 LT1222 Input 1 2 1 2 2 3 2 3 JP4 1x3 Photodiode Bias 1 2 1 2 1 2 1 2 JP5 1x3 Integrator Output 1 2 Out 2 3 Out JP6 1x3 Integrator Input 1 2 2 3 1 2 2 3 JP7 1x2 LT1222 Compensation Out Out In In JP8 1x2 LT1222 Input Out In Out Out Figure 1 Proper Supply Connections Board Is Shown for Source Follower with Integrator In JP1 th...

Page 4: ...ve Input Offset Voltage Is One JFET VGS About 400mV The Source Follower Configuration Is the Simplest and Most Versatile but the JFET In Gain Configuration Offers the Highest Achievable Gain Bandwidth Product and the Lowest Voltage Noise Output Noise at Low and Medium Frequencies 10kHz to 100kHz Is 130nV Hz Dominated Entirely by the Feedback Resistor Figure 3 The Two Basic Types of JFET Configurat...

Page 5: ...om its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices SCHEMATIC DIAGRAM 5 5 4 4 3 3 2 2 1 1 D D C C B B A A TECHNOLOGY GLEN B TECHNOLOGY GLEN B TECHNOLOGY GLEN B JP8 JP8 J1 J1 JP6 JP6 JP7 JP7 Figure 4 DC1416 Demo Circuit Schematic Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 6: ...y for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board inc...

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