Analog Devices LT1222 Demo Manual Download Page 4

4

dc1416fa

DEMO MANUAL DC1416

DC1416 F02

+

LT1222

2V

+12V

–12V

R3

2.49k

D

S

G

V

OUT

NXP

BF862

R1

1MΩ

–12V

+

LT1222

+12V

–12V

R7

3.01k

D

S

G

V

OUT

NXP

BF862

R1

1MΩ

SOURCE FOLLOWER

JFET IN GAIN

+

DC1416 F03

+

LT1222

2V

+12V

–12V

R3

2.49k

R6

221Ω

R11

10MΩ

R11

10MΩ

D

S

G

V

OUT

NXP

BF862

R1

1MΩ

R10

1k

C9

10nF

C9

10nF

–12V

+

LT1222

+

LT1793

LT1793

+12V

–12V

R7

3.01k

D

S

G

V

OUT

NXP

BF862

R1

1MΩ

SOURCE FOLLOWER WITH INTEGRATOR

JFET IN GAIN WITH INTEGRATOR

Figure 2. The Two Basic Types of JFET Configuration. The Left Shows the JFET as a Source 

Follower, Simply Buffering the Feedback Resistor to the Op Amp’s Inverting Input. The Right 

Shows the JFET In Gain, with Source Grounded. Because the JFET Inverts, the Feedback Is Now 

Applied to the Op Amp’s Non-Inverting Input. In Both Cases, the Effective Input Offset Voltage 

Is One JFET V

GS

 (About –400mV). The Source Follower Configuration Is the Simplest and Most 

Versatile, but the JFET In Gain Configuration Offers the Highest Achievable Gain-Bandwidth 

Product and the Lowest Voltage Noise. Output Noise at Low and Medium Frequencies (10kHz to 

100kHz) Is 130nV/

√Hz

, Dominated Entirely by the Feedback Resistor

Figure 3. The Two Basic Types of JFET Configuration Again, but Shown with LT1793 Integrators 

which Zero Out the Overall Input Offset Voltage. On the Left, the JFET V

GS

 Is Forced to the 

LT1793 Non-Inverting Input. On the Right, the Integrator Puts JFET V

GS

 at the Source Directly. 

In both Cases, the 10M Sensing Resistor R11 Injects 40fA/

√Hz

 of Current Noise, which Is 

Discernible but Relatively Small Compared to the 130fA/

√Hz

 of the 1M Feedback Resistor. The 

Output Noise at Low to Medium Frequencies Is about 136nV/

√Hz

Downloaded from

Arrow.com.

Downloaded from

Arrow.com.

Downloaded from

Arrow.com.

Downloaded from

Arrow.com.

Summary of Contents for LT1222

Page 1: ...1793 BF8621 6 pA en Input Voltage Noise Density f 100kHz JFET In Gain Configuration 1 nV Hz en Input Voltage Noise Density f 100kHz Source Follower Configuration 3 nV Hz CIN Input Capacitance f 10kHz Source Follower Configuration 2 pF GBW Gain Bandwidth Product JP In CCOMP 49pF 70 MHz GBW Gain Bandwidth Product JP Out CCOMP 10pF 190 MHz GBW Gain Bandwidth Product JP Out C7 Removed CCOMP 0pF 500 MH...

Page 2: ...w the procedure below 1 With power off connect the 12V 12V and Com leads from the power supply to the V V and GND terminals of the demo circuit as shown in Figure 1 2 With power off connect the VOUT of the demo circuit to an oscilloscope or DMM You can use either the gold SMA connector or the turrets provided on board or both Set a high range such as 2V DIV on the oscil loscope or VDC on the DMM 3...

Page 3: ...1x3 JFET Drain 1 2 1 2 2 3 2 3 JP2 2x3 JFET Source 1 2 1 2 5 6 3 4 JP3 1x3 LT1222 Input 1 2 1 2 2 3 2 3 JP4 1x3 Photodiode Bias 1 2 1 2 1 2 1 2 JP5 1x3 Integrator Output 1 2 Out 2 3 Out JP6 1x3 Integrator Input 1 2 2 3 1 2 2 3 JP7 1x2 LT1222 Compensation Out Out In In JP8 1x2 LT1222 Input Out In Out Out Figure 1 Proper Supply Connections Board Is Shown for Source Follower with Integrator In JP1 th...

Page 4: ...ve Input Offset Voltage Is One JFET VGS About 400mV The Source Follower Configuration Is the Simplest and Most Versatile but the JFET In Gain Configuration Offers the Highest Achievable Gain Bandwidth Product and the Lowest Voltage Noise Output Noise at Low and Medium Frequencies 10kHz to 100kHz Is 130nV Hz Dominated Entirely by the Feedback Resistor Figure 3 The Two Basic Types of JFET Configurat...

Page 5: ...om its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices SCHEMATIC DIAGRAM 5 5 4 4 3 3 2 2 1 1 D D C C B B A A TECHNOLOGY GLEN B TECHNOLOGY GLEN B TECHNOLOGY GLEN B JP8 JP8 J1 J1 JP6 JP6 JP7 JP7 Figure 4 DC1416 Demo Circuit Schematic Downloaded from Arrow com Downloaded from Arrow com Downloaded...

Page 6: ...y for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred damages or any modifications or alterations it makes to the Evaluation Board inc...

Reviews: