Analog Devices EZ-KIT Lite ADSP-BF533, Manual

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ADSP-BF533 EZ-KIT Lite Evaluation System Manual 2-5
Using EZ-KIT Lite
Options dialog box, which is accessible through the Settings pull-down
menu, disables automatic and allows manual configuration. For more
information, see
“Target Options” on page 2-17 .
Automatic configuration of SDRAM is not optimized for any SCLK fre-
quency.
Table 2-3 shows the optimized configuration for the
SDRAM
registers using a 118.8 MHz, 126 MHz, and 133 MHz SCLK. The fre-
quency of 118.8 MHz is the maximum SCLK frequency when using a
594 MHz core frequency, the maximum frequency for the EZ-KIT Lite
when using the internal voltage regulator. Only the
EBIU_SDRRC
register
needs to be modified in the user code to achieve maximum performance.
An example program is included in the EZ-KIT installation directory to
demonstrate how to set up the SDRAM interface.
Using Flash Memory
The following sections describe how to use the memory and general-pur-
pose IO pins, as well as how to configure the Flash memory device.
The ADSP-BF533 EZ-KIT Lite board employs two PSD4256G6V
Flash/General-Purpose IO devices from STMicroelectronics. These
devices not only have Flash memory but also extra IO pins, which are
memory mapped.
Table 2-3. SDRAM Optimum Settings
Register SCLK = 133 MHz
(Processor MAX) SCLK = 126 MHz
(CCLK = 756 MHz) SCLK = 118.8 MHz
(CCLK = 594 MHz)
EBIU_SDGCTL 0x0091 998D 0x0091 998D 0x0091 998D
EBIU_SDBCTL 0x0000 0013 0x0000 0013 0x0000 0013
EBIU_SDRRC 0x0000 0406 0x0000 03CF 0x0000 0397