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UG-580

EVAL-SSM3515Z User Guide

Rev. A | Page 12 of 19

11691-

004

REPLACE WITH

O-OHM

SPDIF_IN

REPLACE WITH

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33

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47K

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3.01K

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47K

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Figure 11. Evaluation Board Digital Input Converter Section

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Summary of Contents for EVAL-SSM3515Z

Page 1: ...g on the information therein All referenced brands product names service names and trademarks are the property of their respective owners 00000005981LF 000 EOS Power Buy Now We have 45 000 LP502030 PCM NTC LD A02554 EEMB Lithium Battery Rectangular 3 7V 250mAh Rechargeable in stock now Starting at 0 034 This EEMB part is fully warrantied and traceable 1 855 837 4225 Give us a call International 1 ...

Page 2: ... 4 5 V to 17 V The board includes 3 3 V and 1 8 V regulators The on board digital SPDIF optical input generates the serial digital signal to the SSM3515 The board provides register control using USBi with SigmaStudio based GUI or the Total Phase Aardvark I2 C SPI Host Adapter The application circuit requires a minimum of external components and can operate from a single 4 5 V to 17 V supply It is ...

Page 3: ...n 4 Regulator Enable 4 Digital Audio Input 4 Input Configuration 4 I2 C Control Port 4 Output Configuration 5 Edge Mode 5 Component Selection 5 Getting Started 6 USBi and SigmaStudio Install 6 Evaluation Board Startup 6 I2 C Writes for Board Startup 10 Evaluation Board Schematics and Artwork 11 Ordering Information 18 Bill of Materials 18 REVISION HISTORY 9 15 Rev 0 to Rev A Change to Figure 1 1 C...

Page 4: ...oise power supply with 4 5 V to 17 V and 5 A current capability The board needs either an optical SPDIF or serial I2 S TDM compatible audio source The board provides the 10 pin header for connecting an external I2 C control device such as the USBi included with the kit or Aardvark I2 C SPI controller via USB to control the internal registers The loudspeaker with 4 Ω to 8 Ω impedance can be connect...

Page 5: ...rd digital audio receiver CS8416 CZZ To make a connection from either the on board audio receiver circuitry or the P2 external digital audio header to the SSM3515 device pins jumpers must be inserted across all three rows of H2 In some use cases such as high speed clocking of data remove the jumpers across H2 to reduce stub length and minimize parasitics In this case source digital audio data on t...

Page 6: ...d in the SSM3515 data sheet remove the output filters and insert a short across L1 and L2 EDGE MODE To reduce the radiated emissions from the SSM3515 amplifier an edge rate control mode is available To enable the reduced EMI mode send an I2 C control register write to activate Bit D4 of Register 0x01 The efficiency is slightly reduced when low EMI mode is enabled To return to the ordinary fast edg...

Page 7: ...udio source for the SDATAI FSYNC and BCLK pins of the SSM3515 If using the SPDIF source select the _INT signal paths on P12 If sourcing via the Audio Precision I2 S TDM output select the _EXT signal paths on P12 and connect digital audio signals via the Audio Precision connection to P2 Note that P5 allows multiple evaluation boards to be daisy chained to the same signal bus 4 Insert jumpers across...

Page 8: ...Figure 5 13 If the I2 C communication failure message appears as shown in Figure 4 the board is not set up correctly a If the yellow light on USBi flickers disconnect and try reconnecting the USB connector from the USBi board b Check if the SCL SDA signal lines at J2 2 and J3 2 are pulled to high c Check the 1 8 V IOVDD on P1 2 If the error persists further debug for I2 C is required before procee...

Page 9: ...ry press the S2 button to reset the SPDIF receiver After reset the BCLK FSYNC and SDATAI signals are available at Header H2 17 If using the Audio Precision PSIA the digital serial signals must be made available at Header P2 18 Click the Chip DAC Control tab in the GUI see Figure 6 This tab provides the power up mute volume control and gain settings 19 Next select the desired analog gain under Amp ...

Page 10: ... J8 and audio can be heard from the connected speaker 21 Click the Chip DAC Control tab in the GUI see Figure 6 Under Master Software Powerdown select Normal Operation to power up the chip 22 The Fault Status tab provides the settings for faults and status see Figure 8 Click Read Status If no faults exist all indicators are green 11691 107 Figure 7 Serial Audio Interface and Limiter Control Tab 11...

Page 11: ...s with the first byte containing the device address followed by the register address followed by register data Figure 9 shows a typical I2 C single word write sequence The default 7 bit device address set on the board is 0x14 If set differently from the default value use that address for the IC address bits Set the subaddress as 0x00 and Data Byte 1 as 0x80 Following the I2 C write the device pull...

Page 12: ...R36 C4 C3 3 5 1 2 4 U2 C9 C8 N P C7 1 PVDD C1 2 1 JP1 2 1 JP2 A C D1 R1 2 1 P23 IOVDD_EXT IOVDD 1V8_REG GBC03SAAN 0 01UF 111 2223 001 111 2223 001 111 2223 001 LT1761ES5 1 8 PBF 10UF 3V3_REG LT1761ES5 3 3 PBF 69157 102HLF EXT_LDO PVDD EXT_LDO LDO_POWER 1K SML DSP1210SIC TR RED 69157 102HLF 470UF 10UF 1UF 0 01UF 1UF 2 2 1UF 10UF 1UF GND GND OUT BYP SHDN_N GND IN GND GND OUT BYP SHDN_N GND IN GND Fi...

Page 13: ... 20 6 23 21 C14 R15 R13 TP11 1 R12 R16 TP1 1 R11 C15 R8 C20 R9 C19 R14 L2 1 2 L3 1 2 L4 1 2 P6 1 2 3 47K 0 1UF 4 3 14 R18 17 16 CS8416_VL R10 9 R5 12 288MEGHZ 33 R6 18 1 C17 2 EG1218 22 CS8416 CZZ 3V3_REG 47K 8416_OMCK R17 10000PF CS8416_VL 47K 47K R4 47K 47K 47K 1000PF R7 47K R19 3V3_REG 7 R23 DNI 10000PF CTP 021 A S Y IOVDD 4 75K 1UF CS8416_RST FSM6JSMA 10 CS8416_RST 11 12 13 25 8416_OMCK S2 3 G...

Page 14: ...6 5 4 3 2 1 P12 10 9 8 7 6 5 4 3 2 1 P5 R38 R39 R33 R37 C30 C22 R28 10 9 8 7 6 5 4 3 2 1 P2 TSW 103 08 G D BCLK FSYNC SDATAI SDATAI_OUT FSYNC_OUT BCLK_OUT TSW 106 08 G D BCLK_OUT SDATAI_OUT LRCLK_BD2 3MN2510 6002RB BCLK_SPDIF LRCLK_SPDIF SDATA_SPDIF MCLK_EXT LRCLK_EXT BCLK_EXT SDATA_EXT BCLK_BD2 SDATAI_BD2 1V8_REG 3V3_REG 3V3_REG 1V8_REG 3V3_REG 1V8_REG FSYNC_OUT FXLP34P5X 0 1UF 0 1UF 33 FXLP34P5X...

Page 15: ...R40 C33 3 2 1 J9 2 1 TP10 TP_BCLK TP9 TP_FSYNC TP8 TP_SDATAI R42 R29 R27 C23 R41 C2 2 2K IOVDD GBC03SAAN GBC03SAAN TSW 103 08 G D BCLK 0 GBC03SAAN REGEN PVDD FSYNC IOVDD GBC03SAAN 250OHMS 0 22UF ADDR BSTP OUT_N OUT_P FSYNC BCLK SCK SDATAI BSTN SDATAI 5V0DD_USB 5V0DD_USB SDA SDA SCK OUT OUT PVDD IOVDD VREG 33PF 53 6 0 0 10UF 100K 2 2K 0 1UF 2 2UF 0 1UF 0 22UF 1UF 3MN2510 6002RB 180OHM 1000PF 180OHM...

Page 16: ... E2 A2 B2 U10 PVDD SSM3515 BSTP VSS BCLK SDATAI OUTP OUTP FSYNC IOVDD PVDD REG_EN SCK OUTN OUTN ADDR SDA BSTN VSS AVSS VREG BSTP BCLK SDATA OUTP FSYNC VREG18 PVDD REG_EN SCL OUTN ADDR SDA BSTN VSS AVSS VREG50 IO IN IO IOIO IO IO IO OUT OUT OUT OUT OUT OUT IN IN IN IN IN IN Figure 14 Evaluation Board Device Pinout ...

Page 17: ... Page 16 of 19 11691 008 Figure 15 Evaluation Board Top Layer Copper 11691 009 Figure 16 Evaluation Board Second Layer Copper 11691 010 Figure 17 Evaluation Board Third Layer Copper 11691 011 Figure 18 Evaluation Board Bottom Layer Copper ...

Page 18: ...EVAL SSM3515Z User Guide UG 580 Rev A Page 17 of 19 11691 012 Figure 19 Evaluation Board Top Silkscreen 11691 013 Figure 20 Evaluation Board Bottom Silkscreen ...

Page 19: ...yellow Connect Tech CTP 021 A S Y 6 J2 J3 J9 P1 P6 J11 Connector PCB wire to board header Molex 22 03 2031 3 P7 JP1 JP2 Connector PCB berg jumper st male 2P 1X M000385 FCI 69157 102HLF 1 M1 MOD photolink fiber optic receiver Everlight PLR135 T9 1 P12 Connector PCB berg header st male 12P SAMTEC TSW 106 08 G D 3 P2 P5 SK1 Connector PCB low profile straight thru hole 2500 series 3M N2510 6002RB 1 R1...

Page 20: ...herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Cust...

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