User Guide
EVALUATION BOARD CONFIGURATION
Rev. 0 | 4 of 9
SETTING UP THE EVALUATION BOARD
The EVAL-ADN4693E-1EBZ allows the ADN4693E-1 to be quickly
and easily evaluated. The EVAL-ADN4693E-1EBZ allows all of the
input and output functions to be exercised without the need for
external components. Jumper configurations are shown in
.
The EVAL-ADN4693E-1EBZ is powered by connecting a 3.3 V
power supply to the VCC and GND connections of the J9 screw
terminal block. The supply current is typically 1 mA with the driver
and receiver disabled. A 10 μF decoupling capacitor, C9, is fitted at
the VCC connector. A 100 nF decoupling capacitor, C1, is included
at the supply pins of the ADN4693E-1, with a placeholder for an
additional capacitor, C3.
The ADN4693E-1 full-duplex transceiver contains both a driver and
receiver that can be individually enabled or disabled via jumper
options. The driver can be enabled or disabled by setting the driver
enable signal, DE, via the LK2 jumper. The receiver can be enabled
or disabled by setting the RE signal, via the LK1 jumper. The DE
and RE signals can also be accessed via the J1-4 screw terminal
block for dynamic control via a processor or a signal generator.
For optimum signal integrity, the ADN4693E-1 digital input signal,
DI, and receiver output signal, RO, are routed to the SMA connec-
tors, J1 and J2, respectively. Alternatively the J1-4 screw terminal
connectors can be used to access the DI and RO signals for easy
wire connections to a microprocessor. The connections to the J1-4
screw terminal block are made via 0 Ω resistors, which can be
removed to eliminate any stub lengths along the interconnect. The
DI input is terminated to GND with a 50 Ω resistor, R3. The RO
trace includes an optional placeholder for a load capacitor at C2.
The M-LVDS input signals, A and B, and M-LVDS output signals,
Y and Z, are accessed via the J5, J6, J8, and J7 SMA connectors,
respectively. These A and B signals and Y and Z signals are routed
as two differential pairs with a differential characteristic impedance
of 100 Ω. The M-LVDS input signals are terminated at the A and
B pins of the ADN4693E-1 with the 100 Ω resistor, RT2. The
M-LVDS output signals are terminated at the Y and Z pins of the
ADN4693E-1 with the 100 Ω resistor, RT1.
An example evaluation of the ADN4693E-1 driver and receiver is
. A signal generator is connected to the DI pin via
the J1 SMA connector, with an input signal of 100 MHz, a 50% duty
cycle, and a swing of between 0 V and 3.3 V. To enable both the
driver and the receiver, the LK1 jumper is set to Position C, and the
LK2 jumper is set to Position A. The J8 SMA connector for Pin Y
is connected to the J5 SMA connector for Pin A, and the J7 SMA
connector for Pin Z is connected to the J6 SMA connector for Pin B.
This setup connects the M-LVDS driver and receiver together in a
point to point loopback network. In addition, oscilloscope probes are
connected to the DI, A, B, and RO testpoints.
Figure 2. Example Evaluation of the ADN4693E-1 Driver and Receiver
