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EVAL-ADIN1300FMCZ

UG-1635

Rev. 0 | Page 3 of 30

EVAL-ADIN1300FMCZ WITH OPTIONAL MDIO INTERFACE DONGLE CONNECTED

214

19-

001

Figure 1.

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Summary of Contents for EVAL-ADIN1300

Page 1: ...software and GUI available to download on the ADIN1300 product page DOCUMENTS NEEDED ADIN1300 data sheet GENERAL DESCRIPTION The EVAL ADIN1300FMCZ allows simplified evaluation of the key features of the ADIN1300 robust industrial low latency gigabit 10 Mbps 100 Mbps and 1 Gbps Ethernet physical layer PHY The EVAL ADIN1300FMCZ is powered by a single external 5 V supply rail that can be supplied eit...

Page 2: ...valuation Software 10 GUI Detailed Overview 11 Board Display Showing Connected EVAL ADIN1300FMCZ Hardware 11 User Buttons Section 11 Link Properties Tab 12 Register Access Tab 13 Clock Pin Control Tab 13 Loopback Tab 13 Testmodes Tab 13 Framechecker Tab 14 Cable Diagnostics Tab 14 Activity Window and Linking Status 15 Activity Log Information Section 15 Loading a Script File 16 Troubleshooting 17 ...

Page 3: ...EVAL ADIN1300FMCZ User Guide UG 1635 Rev 0 Page 3 of 30 EVAL ADIN1300FMCZ WITH OPTIONAL MDIO INTERFACE DONGLE CONNECTED 21419 001 Figure 1 ...

Page 4: ...artner and evaluate the performance of the chip In standalone mode power the EVAL ADIN1300FMCZ with a 5 V supply at the EXT_5V connector Alternatively to standalone mode the EVAL ADIN1300FMCZ has an FMC low pin count LPC connector which can be plugged into an FPGA development board When used with an FPGA board the media independent interfaces MIIs clocks and light emitting diodes LEDs can be conne...

Page 5: ...ivity The LED_0 pin is a multifunction pin shared with the PHY_CFG0 pin configuration function Therefore it can be necessary for the voltage level on the LED_0 pin to be set at a certain value at power on and reset to configure the ADIN1300 as required See the ADIN1300 data sheet for more information on the multilevel strapping being used as part of the hardware configuration The LED_0 pin has a t...

Page 6: ...lected as the local board within the GUI The MDIO interface dongle has two push button switches on the underside of the board S5 and S6 as shown in Figure 5 S5 is for download and reboot purposes S6 is used to reset the on board ADuCM3029 BOTTOM TOP S5 S6 21419 006 USB ADuCM3029 Figure 5 Overview of MDIO Interface Dongle CONFIGURATION PINS SETUP The EVAL ADIN1300FMCZ default configuration and conf...

Page 7: ..._CFG0 Default configuration PHY_CFG1 S3 1 or 2 Note that the EVAL ADIN1300FMCZ boards are shipped in pairs with one board set to 1 and the other set to 2 PHY_CFG0 and S4 4 and LED_0 and S1 1 MAC Interface Selection RX_CTL RX_DV CRS_DV MACIF_SEL1 R8 R9 DNI RXC RX_CLK MACIF_SEL0 R27 R28 DNI Using internal pull down resistors results in MAC interface default selection being the reduced gigabit media ...

Page 8: ... uses the FT232RQ for UART to USB communication The MDIO interface dongle requires the installation of drivers for the FTDI chip Locate and install this driver separately These drivers are available at www ftdichip com Drivers CDM CDM21228_Setup zip Ethernet PHY Software GUI Installation To install the Ethernet PHY software GUI take the following steps 1 Launch the installer file to begin the Ethe...

Page 9: ...SETUP To set up the EVAL ADIN1300FMCZ and use it with the Ethernet PHY software GUI take the following steps 1 Connect a 5 V power supply to the EVAL ADIN1300FMCZ via the EXT_5V connector or the 5 V barrel connector 2 Connect the USB cable to the MDIO interface dongle 3 Connect the USB cable to the PC When connecting the EVAL ADIN1300FMCZ to the PC for the first time the drivers are automatically ...

Page 10: ...rite device registers 5 Clock Pin Control tab Controls which clock is applied to the GP_CLK pin and enables the CLK25_REF pin 6 Loopback tab Controls the various loopback modes 7 Test Modes tab Provides access to the various test modes on the device 8 Framechecker tab Configures and enables the frame generator and frame checker 9 Cable Diagnostics tab Provides easy access to the cable diagnostics ...

Page 11: ...d Power Up Click Software Power Down to place the selected device into software power down mode where the analog and digital circuits are placed into a low power state Most clocks are gated off and no link is brought up Click Software Power Down to enable a software power down The button color changes to orange and the button label changes to Software Power Up Click Software Power Up to exit from ...

Page 12: ...ining user controls for the Link Properties tab with the following Advertised subset of controls available in advertised mode The controls include the following Auto Negotiated Advertised Speeds shows the checkbox availability of all autonegotiated advertised speeds available Select and clear the checkboxes as required All speed options are available in this section The default advertised reflects...

Page 13: ...n the right side of the Activity Log section To access this function slide the arrow to the left to expose it see Figure 20 21419 021 Figure 20 Activity Log Section Register Access CLOCK PIN CONTROL TAB Use this tab to control which clock is applied to the GP_CLK pin and to enable the CLK25_REF pin see Figure 21 21419 022 Figure 21 Clock Pin Control Tab LOOPBACK TAB The various loopback modes are ...

Page 14: ...e 24 Overview of Frame Generator and Frame Checker 21419 026 Figure 25 Frame Generator Status and Frame Checker Result CABLE DIAGNOSTICS TAB The cable diagnostic feature allows the user to diagnose issues with the link Various features within the device are available when the link is up which quantify the quality of the link by measuring features such as the mean squared error MSE level and estima...

Page 15: ... code to show the status of the link depending on how the user has configured the device see Figure 31 21419 032 Figure 31 GUI Link Status ACTIVITY LOG INFORMATION SECTION The activity log reports status information and register write issues to the selected EVAL ADIN1300FMCZ board see Figure 32 The activity log captures the activity in the GUI corresponding to the activity on the local PHY which i...

Page 16: ...own Menus The script file is located in the ADIN1300 folder and is named registers_scripts json see Figure 34 21419 035 Figure 34 Script File Location The register commands can be loaded with either the register name or the register address as shown in the simple examples in the file The commands are loaded sequentially Create the sequence of write commands using a text editor Ensure that the exac...

Page 17: ...ace dongle the GUI may not properly establish communications with the MDIO interface dongle The GUI polls for the MDIO interface dongle regularly and if an error in the MDIO interface dongle communications is found it is flagged in the Activity Log section and highlighted in red font as shown in Figure 35 The message also includes a prompt explaining how to resolve the issue In the example shown i...

Page 18: ... than 1 inch in length and individual trace impedance of these tracks must be kept below 50 Ω with a differential impedance of 100 Ω for each pair The same recommendations apply for traces running from the magnetics to the RJ45 connector Impedance must be kept constant throughout Any discontinuities can impact signal integrity Each pair must be routed together with trace widths the same throughout...

Page 19: ...8 C36 C37 C34 C10 C2 C16 C22 C25 C20 R19 C42 Y1 R24 R40 R33 R37 R38 R31 R32 R29 R30 R23 R22 C30 C27 C1 C23 C15 R1 C19 C21 D4 D3 EXT_CLK XTAL_O MDI_1_N MDI_1_P XTAL_I PHY_CFG1_MODE4 AVDD3P3 INT_N CRS AVDD3P3 MDI_0_N MDI_1_P MDI_1_N AVDD3P3 MDI_2_N MDI_3_P MDI_3_N AVDD3P3 XTAL_I LINK_ST GP_CLK RX_ER GP_CLK RX_ER LINK_ST MDIO TX_CTL TX_EN VDD0P9 AVDD3P3 VDDIO XTAL_O RX_CTL RX_DV RXC RX_CLK RXD_0 RXD_...

Page 20: ... 1µF 75Ω 75Ω 0 1µF 75Ω 75Ω GND3 T1 T1 T1 T1 C24 C29 C32 C35 R5 R4 R3 R2 C39 P1 SHIELD CON MDI_2_N MCT0 MCT1 MCT2 CON MDI_3_N TCT0 MDI_0_P MDI_1_N CON MDI_3_P MCT3 MDI_3_P MDI_3_N TCT3 CON MDI_2_P MCT2 MDI_2_P MDI_2_N TCT2 CON MDI_1_P CON MDI_1_N MCT1 MDI_1_P TCT1 MCT0 CON MDI_0_P CON MDI_0_N MDI_0_N TCT0 TCT1 TCT2 TCT3 MCT3 1 3 2 1 22 23 24 6 5 4 19 20 21 9 8 7 16 17 18 12 11 10 13 14 15 8 7 6 5 4...

Page 21: ...APACITORS AS CLOSE AS POSSIBLE TO THE PINS ADP223ACPZ ADP223ACPZ 4 7µF DNI 4 7µF 4 7µF 50kΩ DNI 0Ω 40kΩ 4 7µF DNI 1803277 1803277 1kΩ ADP7105ACPZ 5 0 100kΩ 4 7µF 0 01µF DNI 4 7µF 4 7µF DNI DNI DNI DNI DNI 1kΩ DNI DNI 10nH DNI 0Ω DNI DNI 0Ω DNI 280kΩ 50kΩ 200kΩ 50kΩ 10nH DNI 0Ω DNI DNI DNI 0 01µF 0 01µF 4 7µF 4 7µF 10nH 10nH 280kΩ 50kΩ 4 7µF GND4 C50 C40 P4 C51 R62 C49 R64 L4 DVDD_P R68 DVDD_N E1 C...

Page 22: ...XD_1 RXD_2 3P3 AUX 3P3 AUX 3P3_FPGA VDDIO MDC MDIO MDC_FMC RXD_3 RXD3 TXCLK TXD2 RXD2 TXCTL SW_6 SW_5 IO_SDA SW_4 LED_A MDC_FMC MDIO_FMC SW_2 TXD_2 H1 H40 H2 H37 H38 H34 H35 H31 H32 H28 H29 H25 H26 H22 H23 H19 H20 H16 H17 H13 H14 H10 H11 H7 H8 H39 H36 H33 H30 H27 H24 H21 H18 H15 H12 H9 H6 H3 H4 H5 D34 D33 D31 D30 D29 D1 D26 D27 D23 D24 D20 D21 D17 D18 D14 D15 D11 D12 D8 D9 D39 D37 D28 D25 D22 D19 ...

Page 23: ... 1 1 4 5 3 2 1 1 19 14 15 30 26 2 32 3 18 28 27 29 25 23 13 12 5 20 17 4 PAD 31 6 7 8 9 11 10 21 22 24 16 5 4 3 2 1 G2 G1 3 2 1 8 7 6 4 PAD 5 A C 3 1 4 2 21 4 3 2 1 4 3 2 1 1 1 1 1 1 52 51 47 50 13 12 9 11 10 7 6 49 34 8 1 14 58 57 41 46 5 4 25 3 2 36 35 45 37 55 54 53 56 31 30 33 29 32 44 62 61 59 60 63 PAD 24 26 43 42 38 27 28 15 48 64 39 40 23 22 21 20 19 18 17 16 AC B VCC A GND Y VCC VCCIO CBU...

Page 24: ...UG 1635 EVAL ADIN1300FMCZ User Guide Rev 0 Page 24 of 30 21419 043 Figure 42 Schematic Silkscreen Top 21419 044 Figure 43 Schematic Silkscreen Bottom ...

Page 25: ...EVAL ADIN1300FMCZ User Guide UG 1635 Rev 0 Page 25 of 30 21419 045 Figure 44 Top Layer 21419 046 Figure 45 Layer 2 Ground Layer ...

Page 26: ...UG 1635 EVAL ADIN1300FMCZ User Guide Rev 0 Page 26 of 30 21419 047 Figure 46 Layer 3 Power and Ground Layer 21419 048 Figure 47 Bottom Layer ...

Page 27: ...or 4 7 μF 50 V 10 0805 X7R Murata GRM21BZ71H475KE15L 2 C70 C72 Ceramic capacitors 10 μF 25 V 10 0805 X5R TDK C2012X5R1E106K085AC 2 C71 C77 Ceramic capacitors 8 pF 16 V 0 5 pF 0402 C0G AVX Corporation 0402YA8R0DAT2A 2 C75 C82 Ceramic capacitors 20 pF 16 V 5 0402 C0G AVX Corporation 0402YA200JAT2A 2 C83 C84 Ceramic capacitors 0 47 μF 35 V 10 0603 X7R Taiyo Yuden GMK107B7474KAHT 2 C86 C88 Ceramic cap...

Page 28: ...112 R119 R148 R150 R191 R194 R195 R196 R210 to R213 Resistors 0 Ω 50 V 1 0402 Multicomp SPC MC00625W040210R 4 R72 R74 R113 R144 Resistors 0 Ω 1 0603 Multicomp SPC MC0603WG00000T5E TC 4 R12 R52 R54 R64 Resistors 50 kΩ 0 1 0603 Vishay PNM0603E5002BST5 1 R121 Resistor 1 MΩ 1 0201 Panasonic ERJ 1GNF1004C 1 R122 Resistor 4 7 kΩ 25 V 1 0201 Multicomp SPC MC0201L6F4701SE 6 R123 R124 R130 R131 R135 R136 R...

Page 29: ... with integrated power management and 256 kB of embedded flash memory Analog Devices ADUCM3029BCPZ 1 Y1 25 MHz 10 ppm crystal 10 pF load capacitor Seiko Epson FA 128_25 000000MHZ_10 0 _ 10 10 1 Y2 32 768 kHz 20 ppm crystal 6 pF load capacitor Abracon Corp ABS07 120 32 768KHZ T 1 Y3 26 MHz 30 ppm crystal 10 pF load capacitor ECS INC ECS 260 10 36Q ES TR Table 8 Not Populated Qty Reference Designato...

Page 30: ...ng ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer may not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to...

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