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UG-1067 

EVAL-ADGS1412SDZ User Guide

 

Rev. 0 | Page 4 of 12 

EVALUATION BOARD HARDWARE 

POWER SUPPLIES 

Connector J1 provides access to the supply pins of th

ADGS1412

VDD, GND, and VSS on J1 link to the appropriate pins on the 

ADGS1412

. For dual-supply voltages, the evaluation board can 

be powered from ±4.5 V to ±16.5 V. For single-supply voltages, 
the GND and VSS terminals must connect together and power the 
evaluation board with 5 V to 20 V. Additionally, 3.3 V is supplied to 
the VL pin of th

ADGS1412

 by the SDP when Link LK1 is in 

Position B. When controlling th

ADGS1412

 by another method 

other than the SDP, supply between 2.7 V and 5.5 V to the VL pin 
of th

ADGS1412

 via the EXT_VL screw terminal input on J1. 

LK1 should be in Position A. 

INPUT SIGNALS 

Two screw connectors, J2 and J3, are provided to connect to 
both the source and drain pins of th

ADGS1412

. Additional 

subminiature Version B (SMB) connector pads are available if 
extra connections are required.  

Each trace on the source and drain side includes two sets of 
0603 pads, which can place a load on the signal path to ground. 

A 0 Ω resistor is placed in the signal path and can be replaced 
with a user defined value. The resistor combined with the 0603 
pads can create a simple resistor-capacitor (RC) filter. 

LINK OPTIONS 

A number of link options are provided on the 

EVAL-

ADGS1412SDZ

 board that must be set for the required operating 

conditions before using. Table 1 describes the positions of the 
links to control the evaluation board via the SDP board using a 
PC and external power supplies. The functions of these link 
options are described in detail in Table 2. 

When using the SDP in conjunction with the 

EVAL-

ADGS1412SDZ

, LK1 must be in Position B to avoid damage to 

the SDP. 

Table 1. Link Options for SDP Control (Default) 

Link Number 

Option 

LK1 B 
LK2 B 

 

Table 2. Link Functions 

Link Number 

Function 

LK1 

This link selects the source of the VL voltage supplied to the 

ADGS1412

 

Position A selects EXT_VL from J1. 

 

Position B selects the 3.3 V from the SDP. 

LK2 

This link selects how a hardware reset is performed. 

 

Position A indicates the SW1 push button performs a hardware reset. 

 

Position B indicates the SDP can perform a hardware reset. 

Summary of Contents for EVAL-ADGS1412SDZ

Page 1: ... a serial peripheral interface SPI The SPI has robust error detection features These are cyclic redundancy check CRC error detection invalid read write address detection and serial clock SCLK count error detection It is possible to daisy chain multiple ADGS1412 devices together This enables the configuration of multiple devices with a minimal amount of digital lines The ADGS1412 also supports burs...

Page 2: ...istory 2 ADGS1412 Evaluation Board Layout 3 Evaluation Board Hardware 4 Power Supplies 4 Input Signals 4 Link Options 4 Evaluation Board Software 5 Installing the Software 5 Initial Set Up 5 Block Diagram And Description 6 Memory Map 7 Evaluation Board Schematics and Artwork 8 Ordering Information 12 Bill of Materials 12 REVISION HISTORY 10 2016 Revision 0 Initial Version ...

Page 3: ...EVAL ADGS1412SDZ User Guide UG 1067 Rev 0 Page 3 of 12 ADGS1412 EVALUATION BOARD LAYOUT 15129 001 Figure 1 ...

Page 4: ... side includes two sets of 0603 pads which can place a load on the signal path to ground A 0 Ω resistor is placed in the signal path and can be replaced with a user defined value The resistor combined with the 0603 pads can create a simple resistor capacitor RC filter LINK OPTIONS A number of link options are provided on the EVAL ADGS1412SDZ board that must be set for the required operating condit...

Page 5: ...plug ins appear when opening ACE INITIAL SET UP To set up the evaluation board complete the following steps 1 Connect the evaluation board to the SDP board and connect the SDP board to the computer via a USB cable 2 Power the evaluation board as described in the Power Supplies section 3 Run the ACE application The EVAL ADGS1412SDZ board plug ins appear in the attached hardware section of the Start...

Page 6: ...ard The full screen block diagram shown in Figure 4 describes the functionality of each block 15129 004 F A B D E C Figure 4 EVAL ADGS1412SDZ Block Diagram with Labels Table 3 Block Diagram Functions Label Function A The drop down menus configure SW1 to SW4 as open or closed B The INVALID RW ENABLE SCLK COUNT ENABLE and CRC ENABLE checkboxes enable or disable the error detection features on the SP...

Page 7: ...he Apply Changes button transfers data to the device All changes here correspond to the block diagram for example if the internal register bit is enabled it displays as enabled on the block diagram Any bits or registers that are bold are modified values that have not been transferred to the evaluation board After clicking Apply Changes the data is transferred to the evaluation board 15129 005 Figu...

Page 8: ...UG 1067 EVAL ADGS1412SDZ User Guide Rev 0 Page 8 of 12 EVALUATION BOARD SCHEMATICS AND ARTWORK 15129 007 Figure 7 EVAL ADGS1412SDZ Schematic 1 15129 008 Figure 8 EVAL ADGS1412SDZ Schematic 2 ...

Page 9: ...EVAL ADGS1412SDZ User Guide UG 1067 Rev 0 Page 9 of 12 15129 009 Figure 9 EVAL ADGS1412SDZ Schematic 3 15129 010 Figure 10 EVAL ADGS1412SDZ Silk Screen ...

Page 10: ...UG 1067 EVAL ADGS1412SDZ User Guide Rev 0 Page 10 of 12 15129 011 Figure 11 EVAL ADGS1412SDZ Top Layer 15129 012 Figure 12 EVAL ADGS1412SDZ Layer 2 ...

Page 11: ...EVAL ADGS1412SDZ User Guide UG 1067 Rev 0 Page 11 of 12 15129 013 Figure 13 EVAL ADGS1412SDZ Layer 3 15129 014 Figure 14 EVAL ADGS1412SDZ Bottom Layer ...

Page 12: ...m Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all be considered the confidential and proprietary information of ADI Customer ...

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