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UG-1896 

EVAL-ADAQ23875FMCZ

 User Guide 

 

Rev. 0 | Page 4 of 26 

ANALOG INPUTS  

The SMA connectors on the EVAL-ADAQ23875FMCZ (VIN+ 
and VIN−) provide analog inputs from a low noise, audio 
precision signal source (such as the SYS-2700 or the SYS-x555 
series). There are three options available to feed analog inputs 
directly to the 

ADG774

, the 

ADA4899-1

, and the ADAQ23875, 

as shown in Figure 20. To test the multiplexed functionality 
using the 

ADG774

 (U2) CMOS multiplexer in front of the 

ADAQ23875 (U1), the positive and negative differential inputs 
of the 

ADG774

 are switched continuously to generate a full-

scale step. The optional amplifiers, 

ADA4899-1

 (A2, A3), can 

be set up in a unity-gain configuration driving the 

ADAQ23875

In a default configuration of board, an input signal via VIN+ 
and VIN− can be fed directly to the 

ADAQ23875

 by bypassing 

U2, A2, and A3. 
The EVAL-ADAQ23875FMCZ is factory configured to provide 
the appropriate input signal type, single-ended or fully 
differential, and different gain/attenuation or input range 
scaling. Table 2 lists the necessary jumper positions and link 

options for different configurations. The default board 
configuration presents 4.096 V on the REFBUF pin. The default 
board configuration also presents a buffered 2.048 V (midscale) 
at the VCMO pin of the FDA on the 

ADAQ23875

.  

To evaluate dynamic performance, a fast Fourier transform 
(FFT), integral nonlinearity (INL), differential nonlinearity 
(DNL), or time domain (waveform, histogram) test can be 
performed by applying a very low distortion ac source (see 
Figure 13 to Figure 17). For low input frequency testing below 
100 kHz, it is recommended to use a low noise, audio precision 
signal source (such as the SYS-2700 series) with the outputs set 
to balanced floating. A different precision signal source can be 
used alternatively with additional band-pass filtering. The filter 
bandwidth depends on input bandwidth of interest. 

LINK CONFIGURATION OPTIONS 

Multiple link options must be set correctly for the appropriate 
operating setup before applying the power and signal to the 
EVAL-ADAQ23875FMCZ. Table 2 shows the default link 
positions for the EVAL-ADAQ23875FMCZ. 

Table 2. Link Options for the EVAL-ADAQ23875FMCZ 

Link 

Default 

Function 

Comment 

JP3 

Center to B 

FPGA CNV+ 

Change center to A when using ADC_. 

JP4 

Center to B  

FPGA CNV− 

Change center to A when using ADC_PLL_CNV−. 

JP5 

Center to A 

AMP+ 

Change center to B when using an external supply. 

JP6 

Center to A 

AMP− 

Change center to B when using an external supply. If configured 
to single supply VS− to GND, remove both jumpers (JP6) and 
install R49 (0 Ω). 

JP9 

Center to A 

3.3 V 

Change center to B when using an external 3.3 V supply. 

P1 

Tie Pin 2 and Pin 3 
(connected to GND) 

Two-lane digital output modes 

Digital input that enables two-lane output mode. Use this jumper 
to select either single-lane or two-lane data output mode. The 
default setting is Pin 2 and Pin 3. The Pin 2 and Pin 3 setting 
clocks out all data on the DA± pin. The Pin 1 and Pin 2 setting 
clocks out data alternately on the DA± and DB± pins. 

P2 

No connect 

ADCIN− 

Negative input of an internal ADC. Extra capacitance can be 

added on this pin to reduce the RC filter bandwidth. Optional for 
the 

ADAQ23875

P3 

No connect 

ADCIN+ 

Positive input of an internal ADC. Additional capacitance can be 
added on this pin to reduce the RC filter bandwidth. Optional for 
the 

ADAQ23875

 

P4 

Tie Pin 1 and Pin 2  

PDB_AMP 

Active low. Connect this pin to GND to power-down the fully 
differential ADC driver. Otherwise, connect it to VS+. 

P5 

Not applicable 

SDP-H1 FMC connector 

The EVAL-ADAQ23875FMCz board interfaces to the 

SDP-H1

 

board via a 160-pin connector. 

P6 

Tie Pin 1 and Pin 2 

PDB_ADC 

Digital input that enables the power-down mode. When 
PDB_ADC is low, an internal ADC core enters power-down mode, 
and all circuitry (including the LVDS interface) is shut down. When 
PDB_ADC is high, the device operates normally. Logic levels are 
determined by VIO.  

P7 

0 Ω installed 

−VS for the

ADA4899-1

 (A2, A3) 

Remove 0 Ω to use the external supply for the 

ADA4899-1

 (A2, A3). 

P8 

0 Ω installed 

+VS for the

ADA4899-1

 (A2, A3) 

Remove 0 Ω to use the external supply for the 

ADA4899-1

 (A2, A3). 

 

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Summary of Contents for EVAL-ADAQ23875FMCZ

Page 1: ...ed on signal frequency SOFTWARE NEEDED EVAL ADAQ23875FMCZ ACE plug in SDP H1 driver GENERAL DESCRIPTION The EVAL ADAQ23875FMCZ evaluation board enables simplified evaluation of the ADAQ23875 15 MSPS 16 bit high speed precision µModule data acquisition solution The evaluation board demonstrates the performance of the ADAQ23875 µModule and is a versatile tool for a variety of applications The ADAQ23...

Page 2: ...s 4 Evaluation Board Connectors 5 Software Installation 6 Installing the ACE Software 6 Software Operation 8 Launching the Software 8 Exiting the Software 8 Description of Analysis Window 8 Troubleshooting 15 Connecting the EVAL ADAQ23875FMCZ and the SDP H1 to the PC 15 Verifying the Board Connection 15 Disconnecting the EVAL ADAQ23875FMCZ 15 Board Layout Guidelines 15 Mechanical Stress 16 Evaluat...

Page 3: ...board requires power from a 12 V wall adapter The SDP H1 has a Xilinx Spartan 6 and an ADSP BF527 processor with connectivity to the PC through a USB 2 0 high speed port The controller boards allow the configuration and capture of data on the daughter boards from the PC via a USB The SDP H1 has an FMC low pin count LPC connector with full differential LVDS and singled ended LVCMOS support It also ...

Page 4: ...lying the power and signal to the EVAL ADAQ23875FMCZ Table 2 shows the default link positions for the EVAL ADAQ23875FMCZ Table 2 Link Options for the EVAL ADAQ23875FMCZ Link Default Function Comment JP3 Center to B FPGA CNV Change center to A when using ADC_PLL_CNV JP4 Center to B FPGA CNV Change center to A when using ADC_PLL_CNV JP5 Center to A AMP Change center to B when using an external suppl...

Page 5: ...A_CNV User defined signals connected to FPGA Bank 2 1 2 FPGA_CNV User defined signals connected to FPGA Bank 2 1 2 DA User defined signals connected to FPGA Bank 2 1 DB User defined signals connected to FPGA Bank 2 1 3P3V_FMC 3 3 V 3 A power supply to daughter board SCL I2 C clock line for reading FMC EEPROM SDA I2 C data line for reading FMC EEPROM GA0 I2 C geographical Address 0 Must be connecte...

Page 6: ...e ACE software take the following steps 1 Download the ACE software to a Windows based PC 2 Double click the ACEInstall exe file to begin the installation By default the software is saved to the following location C Program Files x86 Analog Devices ACE 3 A dialog box appears asking for permission to allow the program to make changes to the PC Click Yes to begin the installation process 4 Click Nex...

Page 7: ...07 Figure 7 Windows Security Window 25385 008 Figure 8 Installation in Progress 9 The installation is complete see Figure 9 Click Next and then click Finish to complete the installation Figure 9 Installation Complete Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 8: ...tart a data capture that gathers samples continuously with one batch of data at a time Results Pane The Display Channels section allows the user to select which channels to capture The data for a specific channel is only shown if that channel is selected before the capture The Waveform Results section displays amplitude sample frequency and noise analysis data for the selected channels Click Expor...

Page 9: ...and if the fundamental is set manually The Windowing section allows the user to set up the preferred windowing type to use in the FFT analysis and the number of harmonic bins and fundamental bins that must be included in the analysis The Single Tone Analysis and the Two Tone Analysis sections sets up the fundamental frequencies included in the FFT analysis When one frequency is analyzed use the Si...

Page 10: ...ADAQ23875FMCZ Board View Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 11: ...Figure 13 EVAL ADAQ23875FMCZ Waveform Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 12: ...L ADAQ23875FMCZ FFT Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 13: ...DNL Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 14: ...d from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com ...

Page 15: ... the PC properly Analog Devices SDP H1 appears under ADI Development Tools in the Device Manager window as shown in Figure 19 Figure 19 Windows Device Manager DISCONNECTING THE EVAL ADAQ23875FMCZ Always remove power from the SDP H1 board or click the reset tact switch located along the mini USB port before disconnecting the EVAL ADAQ23875FMCZ from the SDP H1 board BOARD LAYOUT GUIDELINES The print...

Page 16: ...s no significant performance impact MECHANICAL STRESS The mechanical stress of mounting a device to a board may cause subtle changes to the SNR and internal voltage reference The best soldering method is to use IR reflow or convection soldering with a controlled temperature profile Hand soldering with a heat gun or a soldering iron is not recommended Downloaded from Arrow com Downloaded from Arrow...

Page 17: ... 2 3 L2 L1 K2 K1 J2 H2 H1 G2 G1 B2 B1 A2 A1 E2 E1 D2 D1 C2 L7 L6 L5 A7 A6 A5 H7 D7 J7 C7 F4 F3 K7 B7 G7 E7 H6 D6 L4 L3 K6 K5 K4 K3 J6 J5 J4 J3 H5 H4 H3 G5 G4 G3 F7 F6 F5 F2 F1 E5 E4 E3 D5 D4 D3 C6 C5 C4 C3 B6 B5 B4 B3 A4 A3 J1 C1 G6 E6 7 1 8 4 3 2 6 PAD 5 9 7 10 6 8 3PAD 1 5 2 4 NC NC NC NC VIN GND TP VOUT OUT GND VOUT_F VOUT_S GND GND GND VIN SHDN_N VOUT SENSE ADJ EN GND VIN VIN2 VIN2 VIN2 GND GN...

Page 18: ...2 D1 C10 C9 C8 C7 C6 C3 C1 B9 B7 B6 B5 B4 A9 A7 A6 A5 A4 2 1 2 1 3 2 1 3 2 1 3 2 1 1 3 2 4 3 2 4 1 J1 C5 H1 E4 C4 A8 K6 D6 B8 K7 D9 K3 J4 J3 B1 K5 F2 F1 C2 B2 A2 B3 A3 A1 H10 G10 K8 K9 K10 J10 B10 A10 E10 D10 2 3 2 3 1 1 7 6 5 4 PAD 3 2 1 8 7 6 5 4 PAD 3 2 1 8 INV VOUT VNEG VNEG NINV FEEDBACK DISABLE_N VS_POS PAD INV VOUT VNEG VNEG NINV FEEDBACK DISABLE_N VS_POS PAD PAD S1A IN VDD EN_N S4A S4B D4 ...

Page 19: ...3P3V VADJ 2P5V 3P3V 3P3V 3P3V 4 5 3 1 2 4 5 1 3 2 8 3 5 7 4 2 1 6 1 5 1 5 4 4 3 3 2 2 5 4 3 2 1 1 5 4 3 1 1 10 6 4 7 5 8 9 3 2 30 29 26 24 21 20 17 4 1 6 5 7 8 9 10 11 12 13 14 15 16 25 32 PAD 18 19 22 23 27 28 31 3 2 VCC Y GND NC A VCC Y GND NC A VCC PR_N CLR_N Q GND Q_N D CP SEC PRI VCCB B0 B1 OE_N T R1 GND T R0 A1 A0 VCCA OUT VDD GND NC OUT2 OUT2B S10 PAD RSET GND OUT0 OUT0B OUT1 OUT1B S9 S8 S7...

Page 20: ...C30 C29 C28 C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 G40 G39 G38 G37 G36 G35 G34 G33 G32 G31 G30 G29 G28 G27 G26 G25 G24 G23 G22 G21 G20 G19 G18 G17 G16 G15 G14 G13 G12 G11 G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 H40 H39 H38 H37 H36 H35 H34 H33 H32 H31 H30 H29 H28 H27 H26 H25 H24 H23 H22 H21 H20 H19 H18 H17 H16 H15 H14 H13 H12 H11 H10 H9 H8 H7 H6 H5...

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Page 23: ...aded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from Arrow com Downloaded from ...

Page 24: ... X5R C1608X5R1A106K080AC TDK 1 C76 10 pF multilayer ceramic capacitor C0G C1608C0G1H100D080DA TDK 1 C77 22 µF ceramic capacitor X5R C1608X5R0J226M080AC TDK 1 C8 10 µF v X7R C3216X7R1V106M160AC TDK 1 DS2 LED green clear QTLP600C4TR Fairchild Semiconductor 1 E1 600 Ω at 100 MHz inductor chip ferrite bead MPZ2012S601AT000 TDK 5 E2 E3 E4 E5 E6 30 Ω at 100 MHz inductor chip ferrite bead BLM15PD300SN1D ...

Page 25: ... Ultra low noise high accuracy voltage reference ADR4520ARZ Analog Devices 1 U4 Low noise CMOS LDO linear regulator ADP7118AUJZ 2 5 R7 Analog Devices 1 U5 0 25 ppm noise low drift precision reference 4 096 V out LTC6655BHMS8 4 096 PBF Analog Devices 1 U6 Dual SEPIC inverting µModule dc to dc converter LTM8049EY PBF Analog Devices 1 U7 Ultra low noise high PSRR LDO adjustable voltage output ADP7183...

Page 26: ...tions or alterations it makes to the Evaluation Board including but not limited to soldering or any other activity that affects the material content of the Evaluation Board Modifications to the Evaluation Board must comply with applicable law including but not limited to the RoHS Directive TERMINATION ADI may terminate this Agreement at any time upon giving written notice to Customer Customer agre...

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