Preliminary Technical Data
EVAL AD5933-U1
Rev. PrA | Page 3 of 16
EVALUATION BOARD HARDWARE
TERMINAL BLOCK FUNCTIONS
Table 1.
Pin Name
Description
J1-1
VDD-REF
Terminal Block. ADP3303 Voltage Regulator Input Connection. DVDD-REF is decoupled to the analog ground
plane AGND (J1-2) via standard 0.1 µF and 10 µF suppression capacitors.
J1-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J1-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
J2 -1
DVDD_5v
Terminal Block. AD5933 Digital Circuitry Supply Connection. This connector is decoupled to the digital ground
plane via standard 0.1 µF and 10 µF suppression capacitors. This connector also supplies the high performance
16 MHz surface-mount crystal with the required operating supply voltage.
J2-2 DGND
Terminal Block. Digital Ground Connection. Decoupled to J2-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
J8-1 VDD-AMP
Terminal Block. There is a facility to place a single-supply operational amplifier on the output voltage terminal
(Pin 6) of the AD5933. This terminal block is a connection to the single-supply positive rail of the operation
amplifier. The connector is decoupled to the analog ground plane via standard 0.1 µF and 10 µF suppression
capacitors.
J8-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J8-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board
J9-1 AVDD-REF
Terminal Block. AD5933 Analog Circuitry Reference Input Supply. AVDD-REF is decoupled to the analog ground
plane AGND (J9-2) via standard 0.1 µF and 1 0 µF suppression capacitors.
J9-2 AGND
Terminal Block. Analog Ground Connection. Decoupled to J8-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board
J10-1 AVDD-SIG
Terminal Block. AD5933 Analog Circuitry Input Supply. AVDD-REF is decoupled to the analog ground plane
AGND (J9-2) via standard 0.1 µF and 10 µF suppression capacitors.
J10-2 AGND Terminal Block. Analog Ground Connection. Decoupled to J10-1 using standard 0.1 µF and 10 µF suppression
capacitors. The analog ground plane is connected to the digital ground plane at a single point underneath the
board.
LINK FUNCTIONS
Table 2.
Link No.
Function
LK1
Selects the output of the optional operational amplifier U1. Used to amplify the output excitation voltage from the AD5933
and which is available at SMB connector, TF1_OUT. This link is used in conjunction with Link 6. When Link 1 is inserted, Link 6
(LK6) should be removed and vice versa.
When this link is inserted, the output of the user-supplied amplifier is applied to the SMB output, TF1_OUT.
When this link is removed, the output of the user-supplied amplifier is not applied to the SMB output, TF1_OUT.
LK2
This link option is used to connect the output excitation signal from Pin 6 of the AD5933 to the noninverting terminal of the
user-supplied operational amplifier. This link is used in conjunction with Link 6. When Link 2 is inserted, Link 6 should be
removed and vice versa.
When this link is inserted, the output of the AD5933 excitation voltage pin (Pin 6) is applied to the noninverting terminal (Pin 3
of U1) of the user-supplied operational amplifier.
When this link is removed, the output of the AD5933 excitation voltage pin (Pin 6) is no longer applied to the noninverting
terminal (Pin 3 of U1) of the user-supplied operational amplifier.
LK3
The AD5933 can have an external 16 MHz clock signal or can be clocked internally using the internal RC oscillator. A high
performance 16 MHz surface-mount crystal is supplied with the evaluation board. However, the user can override this clock
signal by applying another system clock signal through the SMB connector CLK1. The surface-mount crystal has to be
removed when an external clock signal is being applied through CLK1.
When this link is inserted, the external clock applied to SMB connector CLK1 is routed to the external clock pin (Pin 8) of the
AD5933.
When this link is removed, the external clock applied to SMB connector CLK1 is not routed to the external clock pin (Pin 8) of
the AD5933. The surface-mount crystal is still connected.
