Analog Devices EVAL-AD5761RSDZ Page 8 User Manual Download | Manualshive

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UG-1151

EVAL-AD5761RSDZ

User Guide

Rev. 0 | Page 8 of 17

16

044

-007

Figure 7. Evaluation Software Main Window,

Configure

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Summary of Contents for EVAL-AD5761RSDZ

Page 1: ...lution utilizing the ADP5070 switching regulator and linear regulators ADP7142 ADP7182 to generate a bipolar supply of up to 13 V and 23 2 V from a single supply as low as 3 V The 3 V input voltage is supplied with a linear power supply via the on board connector PVIN_3V 15V through the USB port connector USB_ POWER or from the SDP B controller board The bipolar supply generated by the power solut...

Page 2: ...e 3 Power Supplies and Default Link Options 3 Power Solution ADP5070 Single Supply Option 4 Bench Power Supply Dual Supply Option 4 On Board Connectors 6 Evaluation Board Software 7 Software Installation 7 Software Operation 7 Main Window 7 Evaluation Board Schematics and Artwork 10 Ordering Information 16 Bill of Materials 16 REVISION HISTORY 8 2017 Revision 0 Initial Version ...

Page 3: ...itors Each device supply pin is again decoupled with a 10 µF and 0 1 µF capacitor pair to the relevant ground plane The analog and digital planes are connected at one location close to the DAC To avoid ground loop problems do not connect AGND and DGND elsewhere in the system Table 1 Quick Start Jumper Configuration for On Board ADP5070 Bench Supply and USB Port Link No ADP5070 with LDOs ADP5070 Be...

Page 4: ...LK14 must be removed to enable both the positive and negative outputs on the ADP5070 See Table 2 for full link options USB Port Supply The EVAL AD5761RSDZ is supplied through the USB_POWER connector via a USB mini B cable No extra voltage supplies are required for the board to operate Note that the LK2 link must be removed for the USB port to be the only supply source Also note that Link LK14 must...

Page 5: ...C Position B selects the source from the negative voltage generated by the ADP5070 when the LK_VOUT link is shorted to Position B If the LK_VOUT link is shorted to Position A the source comes from an externally applied voltage at VS of J4 LK_DVCC This link selects the source of the digital power supply DVCC Position A selects the source from the positive voltage generated by the ADP5070 and adjust...

Page 6: ... in the range of 3 V to 15 V externally SYNC_IN Switching frequency synchronization connector VOUT DAC output connector VREFIN VREFOUT Internal reference voltage output and external reference voltage input connector USB_POWER USB port connector PMOD Connector J5 Pin Configuration and Descriptions 1 2 3 4 5 6 7 8 9 10 11 12 16044 003 Figure 3 Jumper J5 Pin Configuration Table 4 Connector J5 Pin Des...

Page 7: ...ions that appear 16044 004 Figure 4 Connectivity Error Alert MAIN WINDOW The main window of the evaluation software is divided into two tabs Configure and DAC Begin by choosing the device to evaluate the AD5761R 16 bit resolution or the AD5721R 12 bit resolution Note that clicking the AD5721R option allows the user to evaluate the AD5761R as a 12 bit DAC there is no separate evaluation setup for t...

Page 8: ...UG 1151 EVAL AD5761RSDZ User Guide Rev 0 Page 8 of 17 16044 007 Figure 7 Evaluation Software Main Window Configure Tab ...

Page 9: ...EVAL AD5761RSDZ User Guide UG 1151 Rev 0 Page 9 of 17 16044 008 Figure 8 Evaluation Software Main Window DAC Tab ...

Page 10: ...OUT 8 V DD 9 DNC 10 SDO 11 LDAC 12 SDI 13 SYNC 14 SCLK 15 DV CC 16 DGND U1 AD5761RBRUZ TP10 VREFIN VREFOUT C27 0 1µF 2 VIN 6 VOUT 4 GND U6 ADR4525BRZ TP2 VOUT TP8 ALERT C13 0 1µF C12 10µF C6 0 1µF C9 0 1µF C36 10nF R41 10kΩ A B LK_REF TP11 TP12 TP13 R19 0Ω TP14 TP15 1 2 R20 1kΩ R15 0Ω C10 10µF C5 10µF SYNC SCLK SDIN SDO LDAC CLR RESET DGND AVDD AVSS DVCC DGND DVCC DVCC1 DVCC1 16044 009 Figure 9 Sc...

Page 11: ...N2 18 SW2 19 PGND 20 SW1 21 EP U7 ADP5070ACPZ 1 2 PVIN_3V 15V TERMINAL BLOCK PCB 3 81mm 2WAY C31 0 1µF C30 10µF C28 10µF C25 2 2µF R29 15 4kΩ SYNC_IN R22 6 65kΩ R26 47 5kΩ LK7 R23 6 98Ω R30 86 6kΩ LK8 R39 39kΩ V V C29 1µF D2 NSR0240HT1G SOD 323 LK14 R33 232kΩ B A SL9 B A SL10 B A SL6 1 VBUS 2 D 3 D 4 IO 5 GND 6 SHLD1 7 SHLD2 8 SHLD3 9 SHLD4 USB_POWER USB MINI B LED_AVDD R17 1 5kΩ LED_AVSS R21 680Ω...

Page 12: ...ND 7 VIN 8 VIN 9 PADDLE U3 ADP7182ACPZ 1 VOUT 2 SENSE ADJ 3 GND 4 EN 5 SS 6 VIN 7 EP GND U2 ADP7142ACPZN 5 0 R7 C22 2 2µF R10 0Ω R12 0Ω C1 2 2µF R7 49 9kΩ B A LK_DVCC J4 1 3 Pin Terminal Block 5mm Pitch J4 2 J4 3 B A LK_VOUT B A LK_AVDD B A LK_VOUT B A LK_AVSS C3 2 2µF C8 2 2µF C21 2 2µF C11 2 2µF AVSS DVCC AVDD VOUT VOUT 5V AVDD_EXT AVSS_EXT AVDD_EXT AVSS_EXT 16044 011 Figure 11 Schematic of the ...

Page 13: ...UART_TX 61 BMODE1 60 RESET_IN 59 UART_RX 58 GND 57 RESET_OUT 56 TWI_A0 55 NC 54 NC 53 NC 52 GND 51 NC 50 NC 49 TMR_C 48 TMR_A 47 GPIO6 46 GND 45 GPIO4 44 GPIO2 43 GPIO0 42 SCL_1 41 SDA_1 40 GND 39 SPI_SEL1 SPI_SS 38 SPI_SEL_C 37 SPI_SEL_B 36 GND 35 SPORT_INT 34 SPI_D3 33 SPI_D2 32 SPORT_DT1 31 SPORT_DR1 30 SPORT_TDV1 29 SPORT_TDV0 28 GND 27 PAR_FS1 26 PAR_FS3 25 PAR_A1 24 PAR_A3 23 GND 22 PAR_CS 2...

Page 14: ...UG 1151 EVAL AD5761RSDZ User Guide Rev 0 Page 14 of 17 16044 013 Figure 13 Component Placement Layout 16044 014 Figure 14 Top PCB Layer Layout ...

Page 15: ...EVAL AD5761RSDZ User Guide UG 1151 Rev 0 Page 15 of 17 16044 015 Figure 15 Top Side PCB Layer Layout ...

Page 16: ...uctor PFL1609 222MEU FEC 2288737 L2 Surface mount power inductor PFL1609 102MEW FEC 2288736 L3 L4 Surface mount power inductors PFL2015 682MEB FEC 2288749 LK2 LK7 LK8 LK14 2 pin 0 1 inch pitch headers and shorting shunts M20 9990246 FEC 1022247 150 411 LK_AVDD LK_AVSS LK_DVCC LK_REF LK_VOUT LK_VOUT 3 pin SIL header and shorting links M20 9990345 M7567 05 FEC 1022248 150410 PVIN_3V 15V 2 way termin...

Page 17: ...permit any Third Party to access the Evaluation Board As used herein the term Third Party includes any entity other than ADI Customer their employees affiliates and in house consultants The Evaluation Board is NOT sold to Customer all rights not expressly granted herein including ownership of the Evaluation Board are reserved by ADI CONFIDENTIALITY This Agreement and the Evaluation Board shall all...

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