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The following design example will show how to build 

unity-gain,  100Hz ƒ

–3dB

 second-order filter

 using 

DC2837A-A or DC2837A. The target specifications for 

both a Bessel and a Butterworth filter with this architec-

ture are provided in Table 2.

Table 2. Target Second-Order Butterworth and Bessel 

Filter Parameters

BUTTERWORTH

BESSEL

k

1

1.274

Q

0.707

0.577

Populate the board with the component values in Table 3, 

according to the following instructions and Figure 8.

Table 3. Sample A

V

 = 1, ƒ

= 100Hz Filter Component Values

BUTTERWORTH

BESSEL

R1

681k

806k

R2

169k

88.7k

Z1

681k

806k

C1

10nF

10nF

C2

2.2nF

2.2nF

Figure 8. Building A Second-Order Active Lowpass 

Filter with DC2837A

1.  Stuff Z6 with 0Ω to tie +IN to GND
2. Remove C11 and R5
3. Stuff C1, leave 

JP2

 connected

OUT

1

3

–IN

JP6

C10

0.1µF

R2

R1

R8

1k

R6

R7

49.9Ω

C1

Z1

JP5

JP2

JP1

R5

C(R5)

Z6

V

+

2

V

ENABLED

DC2837A-B F08

S

4. Replace R1 and R2 with desired values
5. Replace R5 with desired 

capacitor C2

 value

6.  Stuff Z1 with desired value (gain set resistor).
7.  Completely remove both jumper connectors from JP1 

and 

JP5

 (leave open)

8.  Connect center pin 2 of 

JP1

 to pin 2 of 

JP5

7

DEMO MANUAL 

DC2837A-A/DC2837A-B

Rev. 0

OPERATING PRINCIPLES

Summary of Contents for DC2837A-A

Page 1: ...wcasing the micropower zero drift op amp LTC 2063 A option or LTC2066 B option with shut down in an SC70 6 pin package The board is laid out for mostcommonopampapplicationsandleftmostlyunstuffed to maximize flexibility for a wide range of applications The DC2837A includes the SC70 package op amp jump ers unity gain configuration resistors input lowpass fil ters reverse supply protection and supply...

Page 2: ... to a GND turret Set the scaling to 100mV 2ms per division 7 Power up the system A 100Hz 0 5VP P sine wave centered at 0V should appear on the oscilloscope 8 Increase the signal amplitude and observe the signal for clipping as signals reach the supply rails Slew and settling behavior can be evaluated by switching the signal generator to square wave 9 To evaluate shutdown performance move the jumpe...

Page 3: ...4 V V V V V 2 V V V GND SHDN ENABLE SINGLE OR SPLIT SUPPLY DC BIAS DC BIAS FEEDBACK INPUT FILTER EN DIS 1 1 1 1 3 3 3 3 2 2 2 2 SPLIT SINGLE V V DC2837A B F01 S 3 DEMO MANUAL DC2837A A DC2837A B Rev 0 Figure 1 Simplified Generic Schematic QUICK START PROCEDURE Figure 2 Proper Measurement Equipment Setup POWER SUPPLY 2 50V COM SigGen 100 0Hz OSCILLOSCOPE DC2837A B F02 ...

Page 4: ... at IN is desired the resistors at R1 and R2 may be swapped R1 10k R2 0Ω and the capacitor C1 populated with either 33nF for LTC2063 or 6 8nF LTC2066 Jumper JP2 must be installed for C1 to be connected In general to minimize the effect of chopper clock feedthrough signal bandwidths should be limited to at least a decade below the internal chopping frequency which is 5kHz for LTC2063 and 25kHz for ...

Page 5: ...rt ing gain of RFB RG The DC bias added to IN is set by divider Z1 and R1 and the DC bias added to IN is set by divider R9 and R3 Figure 5 Non Inverting Gain R4 may be optionally populated with a resistor equivalent to RG RFB for increased precision over temperature R4 will cancel out IB and potential parasitic thermocouples at the inputs OUT 1 3 IN IN J1 C10 0 1µF R1 0Ω R3 0Ω R2 RG R4 RG RFB R6 0...

Page 6: ...s connected at the inputs can poten tially lead to clock feedthrough appearing in the output especially if the gain setting of the amplifier is not high enough that GBW roll off will naturally attenuate signals at the clock frequency Placing a capacitor in parallel with a large RFB can help filter out this undesired clock signal On this board if RFB is R5 a filter capacitor can be stuffed in Z2 if...

Page 7: ... Filter Component Values BUTTERWORTH BESSEL R1 681k 806k R2 169k 88 7k Z1 681k 806k C1 10nF 10nF C2 2 2nF 2 2nF Figure 8 Building A Second Order Active Lowpass Filter with DC2837A 1 Stuff Z6 with 0Ω to tie IN to GND 2 Remove C11 and R5 3 Stuff C1 leave JP2 connected OUT 1 3 IN JP6 C10 0 1µF R2 R1 R8 1k R6 0Ω R7 49 9Ω C1 Z1 JP5 JP2 JP1 R5 C R5 Z6 0Ω V 2 V ENABLED DC2837A B F08 S 4 Replace R1 and R2...

Page 8: ... not disclose or transfer any portion of the Evaluation Board to any other party for any reason Upon discontinuation of use of the Evaluation Board or termination of this Agreement Customer agrees to promptly return the Evaluation Board to ADI ADDITIONAL RESTRICTIONS Customer may not disassemble decompile or reverse engineer chips on the Evaluation Board Customer shall inform ADI of any occurred d...

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